SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 173

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

21.4
21.4.1
21.5
21.5.1
21.5.2
21.5.3
21.5.4
21.5.5
6249I–ATARM–3-Oct-11
Product Dependencies
Functional Description
I/O Lines
Bus Multiplexing
Pull-up Control
Static Memory Controller
SDRAM Controller
ECC Controller
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control buses and is composed of the following elements:
The EBI0 and EBI1 offers a complete set of control signals that share the 32-bit data lines, the
address lines of up to 26 bits and the control signals through a multiplex logic operating in func-
tion of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
The EBI0_CSA and EBI1_CSA registers in the Chip Configuration User Interface permit
enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller
lines. The pull-up resistors are enabled after reset. Setting the EBIx_DBPUC bit disables the
pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16-D31 lines can
be performed by programming the appropriate PIO controller.
For information on the Static Memory Controller, refer to the Static Memory Controller section.
For information on the SDRAM Controller, refer to the SDRAM section.
For information on the ECC Controller, refer to the ECC section.
• the Static Memory Controller (SMC)
• the SDRAM Controller (SDRAMC)
• the ECC Controller (ECC)
• a chip select assignment feature that assigns an AHB address space to the external devices
• a multiplex controller circuit that shares the pins between the different Memory Controllers
• programmable CompactFlash support logic (EBI0 only)
• programmable NAND Flash support logic
AT91SAM9263
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