SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 179

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

21.5.7
21.5.7.1
21.5.7.2
6249I–ATARM–3-Oct-11
NAND Flash Support
External Bus Interface 0
External Bus Interface 1
External Bus Interfaces 0 and 1 integrate circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
Programming the EBI0_CS3A field in the EBI0_CSA Register in the Chip Configuration User
Interface to the appropriate value enables the NAND Flash logic. For details on this register,
refer to the Bus Matrix Section. Access to an external NAND Flash device is then made by
accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated
as soon as the transfer address fails to lie in the NCS3 address space. See Figure
Signal Multiplexing on EBI Pins” on page 179
forms, refer to the Static Memory Controller section.
Figure 21-7. NAND Flash Signal Multiplexing on EBI Pins
The NAND Flash logic is driven by the Static Memory Controller on the NCS2 address space.
Programming the EBI1_CS2A field in the EBI1_CSA Register in the Chip Configuration User
Interface to the appropriate value enables the NAND Flash logic. For details on this register,
refer to the Bus Matrix Section. Access to an external NAND Flash device is then made by
accessing the address space reserved to NCS2 (i.e., between 0x9000 0000 and 0x9FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS2 signal is active. NANDOE and NANDWE are invalidated
as soon as the transfer address fails to lie in the NCS2 address space. See
179
section.
for more information. For details on these waveforms, refer to the Static Memory Controller
SMC
NWR0_NWE
NCSx
NRD
NAND Flash Logic
for more information. For details on these wave-
NANDOE
NANDWE
AT91SAM9263
Figure 21-7 on page
NANDOE
NANDWE
“NAND Flash
179