SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 193
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SAM9263
Manufacturer Part Number
SAM9263
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9261.pdf
(248 pages)
5.SAM9263.pdf
(1109 pages)
6.SAM9263.pdf
(51 pages)
Specifications of SAM9263
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Can
1
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
NO
External Bus Interface
2
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9263 PDF datasheet #5
- SAM9263 PDF datasheet #6
- Current page: 193 of 1109
- Download datasheet (17Mb)
23.3.1.2
Table 23-5.
Table 23-6.
Table 23-7.
Notes:
23.4
23.4.1
6249I–ATARM–3-Oct-11
27
27
27
26
26
26
Bk[1:0]
1. M0 is the byte address inside a 16-bit half-word.
4. Bk[1] = BA1, Bk[0] = BA0.
Product Dependencies
25
25
25
SDRAM Device Initialization
Bk[1:0]
Bk[1:0]
16-bit Memory Data Bus Width
24
24
24
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
Bk[1:0]
Bk[1:0]
Bk[1:0]
23
23
23
Bk[1:0]
Bk[1:0]
Bk[1:0]
22
22
22
Bk[1:0]
Bk[1:0]
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
21
21
21
Bk[1:0]
1. SDRAM features must be set in the configuration register: asynchronous timings (TRC,
2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength
3. The SDRAM memory type must be set in the Memory Device Register.
4. A minimum pause of 200 µs is provided to precede any signal toggle.
5.
20
20
20
TRAS, etc.), number of columns, rows, CAS latency, and the data bus width.
(DS) and partial array self refresh (PASR) must be set in the Low Power Register.
(1)
1 in the Mode Register and perform a write access to any SDRAM address.
A NOP command is issued to the SDRAM devices. The application must set Mode to
19
19
19
Row[12:0]
Row[11:0]
18
18
18
Row[10:0]
Row[12:0]
Row[11:0]
17
17
17
Row[10:0]
Row[12:0]
Row[11:0]
16
16
16
Row[10:0]
Row[12:0]
Row[11:0]
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
Row[10:0]
14
14
14
13
13
13
12
12
12
11
11
11
10
10
10
9
9
9
8
8
8
7
7
7
Column[10:0]
Column[10:0]
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
6
6
6
Column[8:0]
Column[8:0]
Column[8:0]
AT91SAM9263
Column[7:0]
Column[7:0]
Column[7:0]
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
235
0
0
0
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