AD9266 Analog Devices, AD9266 Datasheet
AD9266
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AD9266 Summary of contents
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... SENSE REF SELECT CLK+ CLK– PRODUCT HIGHLIGHTS 1. The AD9266 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use ...
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... Absolute Maximum Ratings ............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 11 AD9266-80 .................................................................................. 11 AD9266-65 .................................................................................. 13 AD9266-40 .................................................................................. 14 AD9266-20 .................................................................................. 15 Equivalent Circuits ......................................................................... 16 Theory of Operation ...................................................................... 17 Analog Input Considerations .................................................... 17 REVISION HISTORY 04/10—Revision 0: Initial Version Voltage Reference ....................................................................... 19 Clock Input Considerations ...................................................... 20 Power Dissipation and Standby Mode .................................... 22 Digital Outputs ...
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... GENERAL DESCRIPTION The AD9266 is a monolithic, single-channel 1.8 V supply, 16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and- hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range ...
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... Rev Page AD9266-80 Max Min Typ Max 10 Guaranteed ±0.30 +0.05 ±0.30 +1.0 −0.9/+1.7 −0.9/+1.7 −0.6/+1.1 ±6.5 ±6.2 ±3.5 ±2 1.007 0.983 0.995 1.007 2 2.8 2 6.5 0.9 1.3 0.5 1.3 7.5 1.9 1.7 1.8 1.9 3.6 1.7 3.6 57.6 62.5 65.7 6.3 11.6 113 113 124 130 151 44 0 ...
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... Full 25°C 25°C 95 25°C 93 Full 80 25°C 93 Full 25°C 25°C −102 25°C −102 Full −89 25°C −101 Full 25°C 25°C 90 25°C 700 Rev Page AD9266 AD9266-65 AD9266-80 Min Typ Max Min Typ Max 77.9 77.6 77.5 77.3 76.6 76.6 76.6 75.5 72.1 77.7 77.4 77.3 77.1 76.2 76.5 76.6 75.5 69.4 12.6 12.6 12.5 12.5 12.4 12.4 11.2 −96 − ...
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... High Level Output Voltage 0 Low Level Output Voltage 1 Low Level Output Voltage μ Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up. AD9266-20/AD9266-40/AD9266-65/AD9266-80 Temp Min Full Full 0.2 Full GND − 0.3 Full −10 Full −10 Full ...
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... Typ 520 15.38 12.5 7.69 6.25 1.0 1.0 0.1 0 0.1 0 350 350 300 260 N–5 N–5 N–4 N–4 D15 D14 D15 D14 N–5 N–5 N–4 N–4 AD9266 Max Unit 625 MHz 80 MSPS rms Cycles μs ns Cycles ...
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... AD9266 TIMING SPECIFICATIONS Table 5. Parameter Conditions SPI TIMING REQUIREMENTS t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the SCLK CLK t Setup time between CSB and SCLK ...
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... ESD CAUTION Rev Page Airflow Velocity θ θ θ (m/sec 37.1 3.1 20.7 1.0 32.4 2.5 29.1 is specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD9266 Ψ Unit JT 0.3 °C/W 0.5 °C/W 0.8 °C/W ...
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... Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 30, 31 VIN−, VIN+ ADC Analog Inputs. CLK AVDD CLK– MODE/OR AVDD 3 22 DCO AD9266 (MSB) D15_D14 CSB 4 21 TOP VIEW 5 20 D13_D12 SCLK/DFS (Not to Scale D11_D10 SDIO/PDWN 7 ...
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... SNR = 70dB (71dBFS) SFDR = 79.7dBc –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 8. AD9266-80 Single-Tone FFT with –10 SFDR (dBc) –30 IMD3 (dBc) –50 –70 SFDR (dBFS) –90 –110 IMD3 (dBFS) –130 –95 –85 –75 – ...
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... DCS disabled, unless otherwise noted. 100 SFDR (dBc SNR (dBFS 100 INPUT FREQUENCY (MHz) Figure 10. AD9266-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 100 90 SFDR (dBc SNR (dBFS ...
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... FREQUENCY (MHz) Figure 18. AD9266-65 Single-Tone FFT with f 120 100 –65 –60 = 9.7 MHz Figure 19. AD9266-65 SNR/SFDR vs. Input Amplitude (AIN) with f IN 100 Figure 20. AD9266-65 SNR/SFDR vs. Input Frequency (AIN) with = 69 MHz IN ...
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... FREQUENCY (MHz) Figure 22. AD9266-40 Single-Tone FFT with f 120 100 Figure 23. AD9266-40 SNR/SFDR vs. Input Amplitude (AIN) with f = 9.7 MHz 30.6 MHz IN Rev Page SFDRFS SNRFS SFDR SNR 0 –65 –60 –50 –40 –30 –20 INPUT AMPLITUDE (dBFS) – ...
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... FREQUENCY (MHz) Figure 25. AD9266-20 Single-Tone FFT with f 120 100 –90 = 9.7 MHz Figure 26. AD9266-20 SNR/SFDR vs. Input Amplitude (AIN) with 30.6 MHz IN Rev Page AD9266 SFDRFS SNRFS SFDR (dBc) SNR (dBc) –80 –70 –60 –50 – ...
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... AD9266 EQUIVALENT CIRCUITS AVDD VIN± Figure 27. Equivalent Analog Input Circuit AVDD VREF 7.5kΩ Figure 28. Equivalent VREF Circuit AVDD 375Ω SENSE Figure 29. Equivalent SENSE Circuit AVDD 5Ω CLK+ 15kΩ AVDD 15kΩ 5Ω CLK– Figure 30. Equivalent Clock Input Circuit Figure 31. Equivalent D1_D0 to D15_D14 and OR Digital Output Circuit 375Ω ...
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... AD8138, ADA4937-2, and excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9266 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...
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... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9266. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 40). ...
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... SELECT LOGIC SENSE Figure 42. Internal Reference Configuration If the internal reference of the AD9266 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 43 shows how the internal reference voltage is affected by loading. Table 10. Reference Configuration Summary ...
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... Jitter Considerations section. Figure 46 and Figure 47 show two preferred methods for clock- ing the AD9266 (at clock rates up to 625 MHz when using the internal clock divider). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF transformer balun. ® ...
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... The clock input should be treated as an analog signal when aperture jitter may affect the dynamic range of the AD9266. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources ...
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... CLOCK RATE (MSPS) Figure 53. Analog Core Power vs. Clock Rate In SPI mode, the AD9266 can be placed in power-down mode directly via the SPI port using the programmable external MODE pin. In non-SPI mode, power-down is achieved by assert- ing the PDWN pin high. In this state, the ADC typically dissipates 500 μ ...
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... VIN+ − VIN− = +VREF − 1.0 LSB VIN+ − VIN− > +VREF − 0.5 LSB The lowest typical conversion rate of the AD9266 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance may degrade. Data Clock Output (DCO) The AD9266 provides a data clock output (DCO) signal that is intended for capturing the data in an external register ...
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... BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9266 signal path. Perform the BIST test after a reset to ensure that the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath, starting at the ADC block output ...
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... SERIAL PORT INTERFACE (SPI) The AD9266 serial port interface (SPI) allows the user to con- figure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 13 constitute the physical interface between the programming device of the user and the serial port of the AD9266. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9266 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 16). ...
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... BIST enable 0x10 Offset adjust Bit 5 Bit 4 Bit 3 Soft 1 1 reset 8-bit chip ID, Bits[7:0] AD9266 = 0x78 device variants of chip ID) 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Open Open down Open Open Reset PN Reset PN Output test mode, Bits[3:0] (local) ...
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... B6 0x1A USER_PATT1_MSB B15 B14 0x1B USER_PATT2_LSB B7 B6 0x1C USER_PATT2_MSB B15 B14 0x24 BIST signature LSB 0x2A OR/MODE select AD9266-Specific Customer SPI Control Register 0x10 USR2 1 Bit 5 Bit 4 Bit 3 Bit 2 Open Output Open Output disable invert 1.8 V DCO 3.3 V data drive strength drive strength ...
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... AD9266 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions that are controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI at www.analog.com. USR2 (Register 0x101) Bit 3—Enable GCLK Detect Normally set high, this bit enables a circuit that detects encode rates below about 5 MSPS ...
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... APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9266 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9266 strongly recom- mended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD) ...
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... AD9266BCPZRL7-40 –40°C to +85°C AD9266BCPZ-20 –40°C to +85°C AD9266BCPZRL7-20 –40°C to +85°C AD9266-80EBZ AD9266-65EBZ AD9266-40EBZ AD9266-20EBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...