AD9266 Analog Devices, AD9266 Datasheet - Page 28

• Manufacturer Part Number: AD9266
• Description: 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9266

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9266
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Device Index and Transfer Register
0xFF
Program Registers
0x08
0x09
0x0B
0x0D
0x0E
0x10
Register Name
SPI port
configuration
Chip ID
Chip grade
Transfer
Modes
Clock
Clock divide
Test mode
BIST enable
Offset adjust
Bit 7
(MSB)
0
Open
External
Pin 23 mode
input enable
User test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
Bit 6
LSB
first
Speed grade ID, Bits[6:4] (identify
External Pin 23
function when high
00 = full power-
01 = standby
10 = normal mode:
output disabled
11 = normal mode:
output enabled
Offset adjust in LSBs from +127 to −128 (twos complement format)
device variants of chip ID)
down
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Bit 5
Soft
reset
Reset PN
long gen
8-bit device offset adjustment, Bits[7:0] (local)
Open
Open
Bit 4
1
Reset PN
short gen
8-bit chip ID, Bits[7:0]
Open
Open
Rev. 0 | Page 28 of 32
AD9266 = 0x78
Bit 3
1
Open
Output test mode, Bits[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = 1/0 word toggle
1000 = user input
1001 = 1/0 bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
Bit 2
Soft
reset
BIST
INIT
Clock divider, Bits[2:0]
Open
Clock divide ratio:
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Bit 1
LSB first
Open
00 = chip run
10 = standby
11 = chip wide digital
01 = full power-down
reset
Bit 0
(LSB)
0
Transfer
Duty cycle
stabilize
BIST
enable
Default
Value
(Hex)
0x18
Read
only
Read
only
0x00
0x00
0x01
0x00
0x00
0x00
0x00
Comments
The nibbles are
mirrored so that
LSB- or MSB-first
mode registers
correctly, regardless
of shift mode.
Unique chip ID
used to differentiate
devices; read only.
Unique speed
grade ID used
to differentiate
devices; read only.
Synchronously
transfers data from
the master shift
register to the slave.
Determines various
generic modes of
chip operation.
Enable internal
duty cycle stabilizer
(DCS).
The divide ratio is
the value plus 1.
When set, the test
data is placed on
the output pins in
place of normal data.
When Bit 0 is set,
the built-in self-test
function is initiated.
Device offset trim.