AD7195 Analog Devices, AD7195 Datasheet - Page 39

• Manufacturer Part Number: AD7195
• Description: 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation
• Manufacturer: Analog Devices

Specifications of AD7195

• Resolution (bits): 24bit
• # Chan: 4
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

When a channel change occurs, the modulator and filter reset.
The complete settling time is required to generate the first
conversion after the channel change. Subsequent conversions
on this channel occur at 1/f
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input; therefore, it continues to output conversions at
the programmed output data rate. However, it is at least two
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is
processing a conversion, the ADC takes three conversions after
the step change to generate a fully settled result.
The cutoff frequency f
50 Hz/60 Hz Rejection (Sinc
When FS[9:0] is set to 96 and chopping is enabled, the output
data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The
filter response shown in Figure 43 is obtained. The chopping
introduces notches at odd integer multiples of f
notches due to the sinc filter in addition to the notches intro-
duced by the chopping mean that simultaneous 50 Hz and
60 Hz rejection is achieved for an output data rate of 12.5 Hz.
The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB,
assuming a stable master clock.
Figure 42. Asynchronous Step Change in Analog Input (Sinc
CONVERSIONS
f
3dB
CHANNEL
ANALOG
OUTPUT
= 0.24 × f
INPUT
ADC
Figure 41. Channel Change (Sinc
CH A
CHANNEL A
ADC
CH A CH A
3dB
1/
f
ADC
is equal to
ADC
.
4
Chop Enabled)
1/
CH B
f
4
CHANNEL B
ADC
Chop Enabled)
SETTLED
FULLY
CH B
ADC
CH B
4
/2. The
Chop Enabled)
CH B
CH B
Rev. 0 | Page 39 of 44
The 50 Hz/60 Hz rejection can be improved by setting the
REJ60 bit in the mode register to 1. With FS[9:0] set to 96
and REJ60 set to 1, the filter response shown Figure 44
is achieved. The output data rate is unchanged but the 50 Hz/
60 Hz (± 1 Hz) rejection is increased to 83 dB typically.
–100
–120
–110
Figure 44. Sinc
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–110
–100
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
Figure 43. Sinc
0
0
25
4
Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1)
25
4
Filter Response (FS[9:0] = 96, Chop Enabled)
50
FREQUENCY (Hz)
50
FREQUENCY (Hz)
75
75
100
100
125
125
AD7195
150
150