AD6642 Analog Devices, AD6642 Datasheet - Page 21

• Manufacturer Part Number: AD6642
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

DIGITAL OUTPUTS
The AD6642 output drivers are configured to interface with
LVDS outputs using a DRVDD supply voltage of 1.8 V. The
output bits are DDR LVDS as shown in Figure 2. Applications
that require the ADC to drive large capacitive loads or large
fanouts may require external buffers or latches.
As described in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary or twos complement when using the SPI control.
TIMING
The AD6642 provides latched data with a latency of nine clock
cycles. Data outputs are available one propagation delay (t
after the rising edge of the clock signal.
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −V
> +V
= −V
= 0
= +V
REF
REF
REF
REF
− 0.5 LSB
− 0.5 LSB
− 1.0 LSB
Offset Binary Output Mode
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
PD
)
Rev. A | Page 21 of 32
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD6642. These transients can degrade converter dynamic
performance.
The lowest typical conversion rate of the AD6642 is 40 MSPS.
At clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD6642 provides a data clock output (DCO) signal
intended for capturing the data in an external register. The
output data for Channel A is valid when DCO is high; the
output data for Channel B is valid when DCO is low. See
Figure 2 for a graphical timing description.
Twos Complement Mode
1000 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1111
AD6642