AD6642 Analog Devices, AD6642 Datasheet - Page 7
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AD6642
Manufacturer Part Number
AD6642
Description
Dual IF Receiver
Manufacturer
Analog Devices
Datasheet
1.AD6642.pdf
(32 pages)
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Parameter
LOGIC INPUT (PDWN)
DIGITAL OUTPUTS (LVDS)
1
2
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, f
otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
OUT-OF-RANGE RECOVERY TIME
1
2
Pull up.
Pull down.
Conversion rate is the clock rate after the divider.
Wake-up time is dependent on the value of the decoupling capacitors.
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Differential Output Voltage (V
Output Offset Voltage (V
Input Clock Rate
Conversion Rate
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
Pipeline Delay (Latency)
Wake-Up Time
With NSR Enabled
2
1
A
)
2
SKEW
CH
)
OS
)
DCO
PD
)
)
)
J
OD
)
)
S
= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. A | Page 7 of 32
Min
40
3.0
3.2
−0.4
Min
1.22
0
−90
−10
247
1.125
Typ
26
2
26
5
Typ
2.7
1.3
0.13
4.35
4.55
−0.2
9
12
1.2
2
185
Max
2.1
−134
454
1.375
0.6
+10
Max
625
200
5.7
5.9
0
AD6642
Unit
kΩ
pF
V
V
μA
μA
kΩ
pF
mV
V
Unit
MHz
MSPS
ns
ns
ps rms
ns
ns
ns
Cycles
Cycles
μs
Cycles