AD7626 Analog Devices, AD7626 Datasheet

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AD7626

Manufacturer Part Number
AD7626
Description
16-Bit, 10 MSPS, PulSAR Differential ADC
Manufacturer
Analog Devices
Datasheet

Specifications of AD7626

Resolution (bits)
16bit
# Chan
1
Sample Rate
10MSPS
Interface
LVDS,Ser
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p
Adc Architecture
SAR
Pkg Type
CSP

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FEATURES
Throughput: 10 MSPS
SNR: 91.5 dB
16-bit no missing codes
INL: ±0.45 LSB
DNL: ±0.35 LSB
Power dissipation: 136mW
32-lead LFCSP (5 mm × 5 mm)
SAR architecture
16-bit resolution with no missing codes
Zero error: ±1LSB
Differential input range: ±4.096 V
Serial LVDS interface
Reference options
APPLICATIONS
Digital imaging systems
High speed data acquisition
High dynamic range telecommunications receivers
Spectrum analysis
Test equipment
Table 1. Fast PulSAR® ADC Selection
Input Type
Differential (Ground Sense)
True Bipolar
Differential (Antiphase)
Differential (Antiphase)
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
No latency/no pipeline delay
Self-clocked mode
Echoed-clock mode
LVDS or CMOS option for conversion control (CNV signal)
Internal: 4.096 V
External (1.2 V) buffered to 4.096 V
External: 4.096 V
Digital X-ray
Digital MRI
CCD and IR cameras
Resolution (Bits)
16
16
16
18
1 MSPS to <2 MSPS
AD7653
AD7667
AD7980
AD7983
AD7671
AD7677
AD7623
AD7643
AD7982
AD7984
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The AD7626 is a 16-bit, 10 MSPS, charge redistribution
successive approximation register (SAR) based architecture
analog-to-digital converter (ADC). SAR architecture allows
unmatched performance both in noise (91.5 dB SNR) and in
linearity (±0.45 LSB INL). The AD7626 contains a high speed,
16-bit sampling ADC, an internal conversion clock, and an
internal buffered reference. On the CNV edge, it samples the
voltage difference between the IN+ and IN− pins. The voltages
on these pins swing in opposite phase between 0 V and REF.
The 4.096 V reference voltage, REF, can be generated internally
or applied externally.
All converted results are available on a single LVDS self-clocked
or echoed-clock serial interface, reducing external hardware
connections.
The AD7626 is housed in a 32-lead, 5 mm × 5 mm LFCSP with
operation specified from −40°C to +85°C.
IN+
IN–
BAND GAP
1.2V
AD7626
16-Bit, 10 MSPS, PulSAR
FUNCTIONAL BLOCK DIAGRAM
REFIN
2 MSPS to 3 MSPS
AD7621
AD7622
AD7641
©2009–2010 Analog Devices, Inc. All rights reserved.
CAP
DAC
REF VCM
÷2
SAR
Figure 1.
Differential ADC
CLOCK
6 MSPS
AD7625
SERIAL
LOGIC
LVDS
AD7626
www.analog.com
VIO
CNV+, CNV–
D+, D–
DCO+, DCO–
CLK+, CLK–
10 MSPS
AD7626

Related parts for AD7626

AD7626 Summary of contents

Page 1

... All converted results are available on a single LVDS self-clocked or echoed-clock serial interface, reducing external hardware connections. The AD7626 is housed in a 32-lead × LFCSP with operation specified from −40°C to +85°C. 1 MSPS to <2 MSPS 2 MSPS to 3 MSPS AD7653 ...

Page 2

... Changes to Power-Up Section ...................................................... 21 9/09—Revision 0: Initial Version Theory of Operation ...................................................................... 15 Circuit Information .................................................................... 15 Converter Information .............................................................. 15 Transfer Functions ..................................................................... 16 Analog Inputs ............................................................................. 16 Typical Connection Diagram ................................................... 17 Driving the AD7626 ................................................................... 18 Voltage Reference Options ........................................................ 20 Power Supply ............................................................................... 21 Digital Interface .......................................................................... 22 Applications Information .............................................................. 24 Layout, Decoupling, and Grounding ....................................... 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 Rev Page ...

Page 3

... AD7626 Unit Bits μA ns MSPS LSB Bits LSB LSB LSB ppm/°C LSB ppm/°C LSB LSB dBFS dBFS dB ...

Page 4

... Using an external reference. 2 The ANSI-644 LVDS specification has a minimum output common mode (V 3 Power dissipation is for the AD7626 device only. In self-clocked interface mode, 0 dissipated in the 100 Ω terminator. In echoed-clock interface mode, 1 dissipated in two 100 Ω terminators. Test Conditions/Comments Min 1.18 REF @ 25° ...

Page 5

... DCO CLKD − Divide this time by the number of bits ( read giving the maximum CLK± CYC MSB CLKL Rev Page 5 of AD7626 , unless otherwise noted. Max Unit 10,000 100 − )/n ns ...

Page 6

... AD7626 TIMING DIAGRAMS SAMPLE N t CNVH CNV– CNV+ ACQUISITION t CLK CLK– CLK+ t DCO DCO– DCO+ t CLKD D+ N – 1 D– SAMPLE N t CNVH CNV– CNV+ ACQUISITION t CLK 17 CLK– CLK CLKD – 1 D– SAMPLE ...

Page 7

... −0 +2.7 V ESD CAUTION −0 −0 −0 VIO + 0.3 V −0 VIO + 0.3 V ±10 mA −40°C to +85°C −65°C to +150°C 150° Rev Page 7 of AD7626 θ θ Unit °C/W ...

Page 8

... Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. GND VDD1 1 24 PIN 1 IN+ VDD2 2 23 INDICATOR 22 IN– CAP1 3 VCM REFIN 4 AD7626 21 VDD1 EN0 5 20 TOP VIEW VDD1 EN1 6 19 (Not to Scale VDD2 VDD2 8 17 CLK+ CNV– ...

Page 9

... PCB using multiple vias. See the Exposed Paddle section for more information analog input; AI/O = bidirectional analog analog output digital input digital output power. ADR434 or the ADR444, the internal reference buffer must be disabled. In either case, connect Rev Page 9 of AD7626 ...

Page 10

... AD7626 TYPICAL PERFORMANCE CHARACTERISTICS VDD1 = 5 V; VDD2 = 2.5 V; VIO = 2.5 V; REF = 4.096 V; all plots at 10 MSPS unless otherwise noted. FFT plots for 2 MHz, 3 MHz, and 5 MHz input tones use band pass filter (±400 kHz pass bandwidth around fundamental frequency). 0 INPUT FREQUENCY = 10.37kHz SNR = 91.85dB – ...

Page 11

... Figure 15. FFT, 5 MHz, −0.5 dB Input Tone Zoomed View 1MHz –3 0 10k Figure 16. THD and SNR vs. Input Frequency (−0.5 dB Input Tone) Rev Page 11 of AD7626 FUNDAMENTAL THIRD HARMONIC FIFTH HARMONIC 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 FREQUENCY (MHz) FUNDAMENTAL THIRD HARMONIC FIFTH HARMONIC 4.55 4 ...

Page 12

... AD7626 92.0 91.8 91.6 91.4 91.2 EXTERNAL REFERENCE 91.0 90.8 INTERNAL REFERENCE 90.6 90.4 90.2 90.0 –40 – TEMPERATURE (°C) Figure 17. SNR vs. Temperature (−0.5 dB, 20 kHz Input Tone) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –6 –4 –2 0 INPUT COMMON-MODE VOLTAGE (V) Figure 18. Input Current (IN+, IN−) vs. Differential Input Voltage (10 MSPS) –103.0 –103.5 –104.0 EXTERNAL REFERENCE –104.5 – ...

Page 13

... FECD FECE 0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 2329 0 –0.8 FECA FECB 0 Figure 26. Integral Nonlinearity vs. Code vs. Temperature Rev Page 13 of 16,384 32,768 49,152 CODE Figure 25. Differential Nonlinearity vs. Code (25ºC) 16,384 32,768 49,152 CODE AD7626 65,536 +85°C +25°C –40°C 65,536 ...

Page 14

... AD7626 TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency the power of a 100 mV p-p sine wave applied to the common-mode voltage frequency CMRR (dB log(Pf/ where the power at frequency the ADC output. ...

Page 15

... The AD7626 offers the added functionality of a high performance on-chip reference and on-chip reference buffer. The AD7626 is specified for use with 5 V and 2.5 V supplies (VDD1, VDD2). The interface from the digital host to the AD7626 uses 2.5 V logic only. The AD7626 uses an LVDS interface to transfer data conversions. The CNV+ and CNV− ...

Page 16

... V 0x8000 ANALOG INPUTS The analog inputs, IN+ and IN−, applied to the AD7626 must be 180° out of phase with each other. Figure 29 shows an equivalent circuit of the input structure of the AD7626. The two diodes provide ESD protection for the analog inputs, IN+ and IN− ...

Page 17

... CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE THE TRACE TO PIN 19 AND PIN 20 FROM THE TRACE TO PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266. 7 SEE THE DRIVING THE AD7626 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS. 8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS. ...

Page 18

... IS USUALLY A 10µF CERAMIC CAPACITOR WITH LOW ESL AND ESR. REF DECOUPLE REF AND REFIN PINS AS PER THE EN1 AND EN0 RECOMMENDATIONS Figure 33. Driving the AD7626 from a Differential Analog Source Using ADA4899-1 (UNIPOLAR 0V TO 4.096V) Figure 32. Single-Ended-to-Differential Driver Circuit Using ADA4899-1 ...

Page 19

... Figure 34. High Frequency Input Drive Circuit Using the ADA4932-1; Single-Ended-to Differential Configuration C22 C24 0.1µF 0.1µF GND VCM GND +V V 20Ω S OCM 1 FB– 2 +IN 11 –OUT 3 ADA4932-1 –IN 10 +OUT PD 4 20Ω FB+ –V PAD S C15 0.1µF GND Rev Page 19 of AD7626 AD8031 100nF GND 56pF VCM IN– AD7626 IN+ 56pF GND ...

Page 20

... AD7626 VOLTAGE REFERENCE OPTIONS The AD7626 allows flexible options for creating and buffering the reference voltage. The AD7626 conversions refer to 4.096 V only. The various options creating this 4.096 V reference are controlled by the EN1 and EN0 pins (see Table 8). CONNECT 1.2V EXTERNAL REFERENCE TO REFIN PIN. ...

Page 21

... VDD2 can be taken from the same 2.5 V source; however best practice to isolate the VIO and VDD2 pins using separate traces as well as to decouple each pin separately. The 5 V and 2.5 V supplies required for the AD7626 can be generated using Analog Devices, Inc., LDOs such as the ADP3330-2.5, ADP3330-5, ADP3334, and ADP1708. ...

Page 22

... LVDS signal can be applied in the form of a 2.5 V CMOS logic signal to the CNV+ pin. The conversion is initiated by the rising edge of the CNV± signal. After the AD7626 is powered up, the first conversion result generated is invalid. Subsequent conversion results are valid provided that the time between conversions does not exceed the maximum specification for t ...

Page 23

... After a conversion begins, it continues until completion. Additional CNV± pulses are ignored during the conversion phase. After the time, t the CLK± signal to the AD7626. All 18 CLK± pulses are to be applied in the time window framed The required 18 CLK± pulses must finish before t CLKL (referenced to the next conversion phase) elapses ...

Page 24

... Pin 28 by widening the PCB traces connecting these pins. Take a similar approach in the connections used for the reference pins of the AD7626. Connect Pin 29, Pin 30, and Pin 32 together using widened PCB traces to reduce inductance. In internal or external reference mode, a 4.096 V reference voltage is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to Pin 31 using a 10 μ ...

Page 25

... Evaluation Board Converter Evaluation and Development Board Rev Page 0.60 MAX PIN 1 INDICATOR 3.25 EXPOSED PAD 3.10 SQ (BOTTOM VIEW) 2. 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD7626 Package Option CP-32-2 CP-32-2 ...

Page 26

... AD7626 NOTES Rev Page ...

Page 27

... NOTES Rev Page AD7626 ...

Page 28

... AD7626 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07648-0-1/10(A) Rev Page ...

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