AD7153 Analog Devices, AD7153 Datasheet
AD7153
Specifications of AD7153
Available stocks
Related parts for AD7153
AD7153 Summary of contents
Page 1
... The AD7152/AD7153 have four capacitance input ranges per operation mode, ±0. ± differential mode and 0 single-ended mode. The AD7152/AD7153 can accept common-mode capacitance (not changing), which can be balanced by a programmable on-chip, digital-to-capacitance converter (CAPDAC). ...
Page 2
... Timing Specifications .................................................................. 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Serial Interface ................................................................................ 11 Write Operation .......................................................................... 11 Read Operation ........................................................................... 11 AD7152/AD7153 Reset ............................................................. 12 General Call................................................................................. 12 Register Map .................................................................................... 13 Status Register ............................................................................. 14 Data Registers ............................................................................. 15 Offset Calibration Registers ...................................................... 15 Gain Calibration Registers ........................................................ 15 CAP Setup Registers .................................................................. 16 REVISION HISTORY 5/08— ...
Page 3
... V 0.8 V ±0.1 ±5 μA 0.4 V 0.1 5 μA 2.45 2.65 V Rev Page AD7152/AD7153 Test Conditions/Comments Differential mode Single-ended mode 25° 3 range DD 25° 3 range DD 25° 3.3 V, after system offset DD calibration, ±2 pF range Single-ended mode, CIN and EXC pins disconnected, see Figure 8 ...
Page 4
... AD7152/AD7153 Parameter POWER REQUIREMENTS V -to-GND Voltage DD 9 Current Current Power-Down Mode −12 −15 Capacitance units Specification is not production tested but is supported by characterization data at initial product release. 3 Except Channel 2 in differential mode. To achieve the specified performance in differential mode, the I prevent signal coupling from the SCL pin to the adjacent CIN2(− ...
Page 5
... BUF HIGH t t HD;DAT SU;DAT Figure 3. Serial Interface Timing Diagram Rev Page AD7152/AD7153 Unit Test Conditions/Comments See Figure 3. kHz μs μs μs μs μs After this period, the first clock is generated. μs Relevant for repeated start condition. μs μ ...
Page 6
... AD7152/AD7153 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Positive Supply Voltage GND DD Voltage on Any Input or Output Pin to GND ESD Rating (ESD Association Human Body Model, S5.1) ESD Rating (Field-Induced Charged Device Model) Operating Temperature Range Storage Temperature Range ...
Page 7
... EXC2/NC AD7152: CDC Excitation Output for Channel 2. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit. AD7153: No Connect. This pin must be left as an open circuit. 6 EXC1 CDC Excitation Output for Channel 1. The measured capacitance is connected between one of the EXC pins and one of the CIN pins ...
Page 8
... AD7152/AD7153 TYPICAL PERFORMANCE CHARACTERISTICS 0.05 0.04 0.03 0.02 0.01 0 0.01 0.02 0.03 0.04 0.05 –2 –1 0 CAPACITANCE (pF) Figure 6. Capacitance Input Integral Nonlinearity 3.3 V, See Figure 34 DD 0.20 0.15 0.10 0.05 0.00 –0.05 –0.10 –0.15 –0.20 –0. TEMPERATURE (°C) Figure 7. Capacitance Input Gain Drift vs. Temperature 3.3 V, Range = ± 0.4 0.2 0 –0.2 –0.4 –50 – TEMPERATURE (°C) Figure 8 ...
Page 9
... RESISTANCE EXC TO GROUND (MΩ) Figure 14. Capacitance Input Error vs. Parasitic Resistance EXC to GND, Single-Ended Mode, CIN(+) to EXC = 9 pF, VDD = 3.3 V 250 300 350 Figure 15. Capacitance Input Error vs. Parasitic Parallel Resistance 1000 100 1000 Rev Page AD7152/AD7153 10 0 –10 –20 –30 –40 – 100 PARALLEL RESISTANCE (MΩ ...
Page 10
... AD7152/AD7153 –10 –20 – CAPDAC CODE Figure 18. CAPDAC(+) Differential Nonlinearity (DNL –10 –20 – CAPDAC CODE Figure 19. CAPDAC(−) Differential Nonlinearity (DNL Rev Page –20 –40 –60 –80 ...
Page 11
... SDA line for transmission to the master acknowledge is received, the AD7152/AD7153 return to the idle state and the address pointer is not incremented. The autoincrementer of the address pointers allows block data to be written or read from the starting address and subsequent incremental addresses ...
Page 12
... The general call address is for addressing every device connected to the I this address and read the following data byte. If the second byte is 0x06, the AD7152/AD7153 are reset, completely uploading all default values. The AD7152/AD7153 do not respond to the I during the default values upload for approximately 150 μs (maximum 200 μ ...
Page 13
... Unused Unused Ch1en Unused DACPen Unused Unused DACP Bits[4:0] value DACNen Unused Unused DACN Bits[4:0] value Unused Unused OSR1 OSR0 Rev Page AD7152/AD7153 Bit 3 Bit 2 Bit 1 Bit 0 Unused C1C2 RDY2 RDY1 Unused Unused Ch2en MD2 MD1 MD0 Unused Unused Unused ...
Page 14
... AD7152/AD7153 STATUS REGISTER Address 0x00 Read Only Default Value 0x03 This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished conversion. Table 7. Status Register Bit Map Bit Bit 7 Mnemonic PWDN Default 0 Table 8. Status Register Bit Descriptions ...
Page 15
... CDC input to the zero-scale data code. The coefficient can be used for compensation of the AD7152/ AD7153 internal offset as well as the system level offset within specified offset calibration limits. Users can set the coefficient by executing the offset calibration after connecting the zero-scale capacitance to the system input. ...
Page 16
... AD7152/AD7153 CAP SETUP REGISTERS Address 0x0B for Channel 1 Address 0x0E Channel 2 (AD7152 Only) Default Value 0x00 Table 10. CAP Setup Register Bit Map Bit Bit 7 Mnemonic Range 1 Default 0 Table 11. CAP Setup Register Bit Descriptions Bit Mnemonic Description 7 Range 1 Capacitive input range and mode setup ...
Page 17
... Bit 5 Bit 4 Unused OSR1 OSR0 OSR0 Conversion Time (ms Rev Page AD7152/AD7153 Bit 3 Bit 2 Bit 1 DACP – Bits[4:0] Value 0x00 Bit 3 Bit 2 Bit 1 DACN – Bit[4:0] Value 0x00 Bit 3 Bit 2 Bit Update Rate (Hz) 200 ...
Page 18
... I C-compatible serial interface. The AD7153 has one capacitive input, while the AD7152 has two capacitive inputs. For the AD7152, the modulator input and the excitation source are multiplexed between the converting channel. All other features and specifications are identical for both parts ...
Page 19
... CAPDAC The CDC full-scale input range of the AD7152/AD7153 can be set to ±0.25 pF, ±0.5 pF, ± 1 pF, and ± differential mode or 0.5 pF, 1 pF, 2 pF, and single-ended mode. For simplicity, the following text and figures use the maximum full scale of ±2 pF and +4 pF. ...
Page 20
... EXC Figure 34. Using CAPDAC in Differential Mode PARASITIC CAPACITANCE TO GROUND C , between the Y C The CDC architecture used in the AD7152/AD7153 measures C connected between the EXC pin and the CIN pin. In theory, X any capacitance, C result (see Figure 35). 0x0000 ... 0xFFF0 The practical implementation of the circuitry in the chip DATA ± ...
Page 21
... V CAPACITIVE GAIN CALIBRATION The gain of the AD7152/AD7153 is factory calibrated for the full scale the production for each part individually. The factory gain coefficient is stored in a one-time program- mable (OTP) memory and is copied to the capacitive gain registers at power-up or after reset ...
Page 22
... Figure 41. Basic Application Diagram for a Differential Capacitive Sensor calibration coefficient value should be stored by the host controller and reloaded as part of the AD7152/AD7153 setup. Note that the AD7152/AD7153 zero scale for differential mode is around 0x8000; therefore, the offset register also needs a value of around 0x8000, where the zero scale in single-ended mode is 0x0000, with a required offset register value of 0x3000 ...
Page 23
... Figure 42. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Evaluation Board Rev Page AD7152/AD7153 0.80 8° 0.60 0° 0.40 Package Option RM-10 RM-10 RM-10 ...
Page 24
... AD7152/AD7153 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...