AD7148 Analog Devices, AD7148 Datasheet - Page 23

• Manufacturer Part Number: AD7148
• Manufacturer: Analog Devices

Specifications of AD7148

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

Figure 33. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 30, there are a number of FIFOs implemented
on the AD7148. These FIFOs are located in Bank 3 of the on-chip
memory. The slow FIFOs are used by on-chip logic to monitor
the ambient capacitance level from each sensor.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12]are the slow FIFO skip control
for full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP. These values determine which CDC samples
are not used (skipped) in the slow FIFO. Changing theses values
slows down or speeds up the rate at which the ambient capacitance
value tracks the measured capacitance value read by the converter.
Equations for On-Chip Logic Stage High and Logic Stage Low Threshold Calculation
NOTES
1. INITIAL STAGEx_OFFSET_HIGH REGISTER VALUE.
2. POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
3. POSTCALIBRATED REGISTER STAGEx_HIGH_THRESHOLD.
4. INITIAL STAGEx_LOW_THRESHOLD.
5. POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
6. POSTCALIBRATED REGISTER STAGEx_LOW_THRESHOLD.
STAGEx_HIGH_THRESHOLD = STAGE_SF_AMBIENT +
STAGEx_LOW_THRESHOLD = STAGE_SF_AMBIENT +
CHANGING ENVIRONMENTAL CONDITIONS
⎛
⎜
⎜
⎜
⎜
⎝
⎛
⎜
⎜
⎜
⎜
⎝
1
4
STAGEx
STAGEx
SENSOR 2 INT
ASSERTED
_
_
OFFSET
OFFSET
SENSOR 1 INT
2
5
ASSERTED
_
_
HIGH
LOW
16
16
−
−
3
6
STAGEx
STAGEx
t
STAGEx_HIGH_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
CDC AMBIENT
VALUE DRIFTING
STAGEx_LOW_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
_
_
OFFSET
OFFSET
4
4
_
_
HIGH
LOW
Rev. A | Page 23 of 56
⎞
⎟
⎟
⎟
⎟
⎠
⎞
⎟
⎟
⎟
⎟
⎠
× POS_THRESHOLD_SENSITIVITY
× POS_THRESHOLD_SENSITIVITY
⎛
⎜
⎝
⎛
⎜
⎝
STAGEx
STAGEx
Slow FIFO update rate in full power mode is equal to
Slow FIFO update rate in low power mode is equal to
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples from
the converter at a rate of 25 ms. AVG_FP_SKIP and AVG_LP_
SKIP are used to normalize the frequency of the samples going into
the FIFO, regardless of how many conversion stages are in a
sequence.
Determining the AVG_FP_SKIP and AVG_LP_SKIP values is
required only once during the initial setup of the capacitance
sensor interface. When using all eight conversion stages,
recommended values for these settings are
SLOW_FILTER_UPDATE_LVL
The SLOW_FILTER_UPDATE_LVL (Address 0x003[15:14])
controls whether the most recent CDC measurement goes into
the slow FIFO (slow filter) or not. The slow filter is updated
when the difference between the current CDC value and last
value pushed into the slow FIFO is greater than SLOW_FILTER_
UPDATE_LVL.
_
_
OFFSET
OFFSET
AVG_FP_SKIP × [(3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM +1) ×
(FF_SKIP_CNT +1) × 4x10
AVG_FP_SKIP = 00 = skip 3 samples
AVG_LP_SKIP = 00 = skip 0 samples
(AVG_LP_SKIP +1) × [(3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) ×
4x10
4
4
−7
]/[(FF_SKIP_CNT +1 ) + LP_CONV_DELAY]
_
_
LOW
HIGH
⎞
⎟
⎠
⎞
⎟
⎠
+
+
−7
]
AD7148
(1)
(2)