AD7148 Analog Devices, AD7148 Datasheet - Page 41

• Manufacturer Part Number: AD7148
• Manufacturer: Analog Devices

Specifications of AD7148

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 250kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

Table 26. STAGEx_HIGH_LIMIT_INT Register
Address
0x009
1
Table 27. STAGEx_COMPLETE_INT_STATUS Register
Address
0x00A
1
Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Data
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[15:8]
Data
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[15:8]
Default
Value
0
0
0
0
0
0
0
0
Default
Value
0
0
0
0
0
0
0
0
Type
R
R
R
R
R
R
R
R
Type
R
R
R
R
R
R
R
R
Mnemonic
STAGE0_HIGH_LIMIT_INT
STAGE1_HIGH_LIMIT_INT
STAGE2_HIGH_LIMIT_INT
STAGE3_HIGH_LIMIT_INT
STAGE4_HIGH_LIMIT_INT
STAGE5_HIGH_LIMIT_INT
STAGE6_HIGH_LIMIT_INT
STAGE7_HIGH_LIMIT_INT
Unused
Mnemonic
STAGE0_COMPLETE_INT_STATUS
STAGE1_COMPLETE_INT_STATUS
STAGE2_COMPLETE_INT_STATUS
STAGE3_COMPLETE_INT_STATUS
STAGE4_COMPLETE_INT_STATUS
STAGE5_COMPLETE_INT_STATUS
STAGE6_COMPLETE_INT_STATUS
STAGE7_COMPLETE_INT_STATUS
Unused
1
1
Rev. A | Page 41 of 56
Description
STAGE0 CDC conversion high limit interrupt result
STAGE1 CDC conversion high limit interrupt result
Stage2 CDC conversion high limit interrupt result
STAGE3 CDC conversion high limit interrupt result
STAGE4 CDC conversion high limit interrupt result
STAGE5 CDC conversion high limit interrupt result
STAGE6 CDC conversion high limit interrupt result
STAGE7 CDC conversion high limit interrupt result
Set unused register bits to 0
Description
STAGE0 conversion complete register interrupt status
STAGE1 conversion complete register interrupt status
STAGE2 conversion complete register interrupt status
STAGE3 conversion complete register interrupt status
STAGE4 conversion complete register interrupt status
STAGE5 conversion complete register interrupt status
STAGE6 conversion complete register interrupt status
STAGE7 conversion complete register interrupt status
Set unused register bits to 0
1 = indicates STAGE0 conversion completed
1 = indicates STAGE1 conversion completed
1 = indicates STAGE2 conversion completed
1 = indicates STAGE3 conversion completed
1 = indicates STAGE4 conversion completed
1 = indicates STAGE5 conversion completed
1 = indicates STAGE6 conversion completed
1 = indicates STAGE7 conversion completed
1 = indicates STAGE0_HIGH_THRESHOLD value exceeded
1 = indicates STAGE1_HIGH_THRESHOLD value exceeded
1 = indicates STAGE2_HIGH_THRESHOLD value exceeded
1 = indicates STAGE3_HIGH_THRESHOLD value exceeded
1 = indicates STAGE4_HIGH_THRESHOLD value exceeded
1 = indicates STAGE5_HIGH_THRESHOLD value exceeded
1 = indicates STAGE6_HIGH_THRESHOLD value exceeded
1 = indicates STAGE7_HIGH_THRESHOLD value exceeded
AD7148