AD7765 Analog Devices, AD7765 Datasheet - Page 15

• Manufacturer Part Number: AD7765
• Description: 24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7765

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: 6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

THEORY OF OPERATION
The AD7765 features an on-chip fully differential amplifier to
feed the Σ-Δ modulator pins, an on-chip reference buffer, and a
FIR filter block to perform the required digital filtering of the
Σ-Δ modulator output. Using this Σ-Δ conversion technique
with the added digital filtering, the analog input is converted
into an equivalent digital word.
Σ-Δ MODULATION AND DIGITAL FILTERING
The input waveform applied to the modulator is sampled, and
an equivalent digital word is output to the digital filter at a rate
equal to ICLK. By employing oversampling, the quantization
noise is spread across a wide bandwidth from 0 to f
means that the noise energy contained in the signal band of
interest is reduced (see Figure 23). To further reduce the
quantization noise, a high order modulator is employed to
shape the noise spectrum so that most of the noise energy is
shifted out of the signal band (see Figure 24).
Table 6. Configuration with Default Filter
ICLK
Frequency
20 MHz
20 MHz
12.288 MHz
12.288 MHz
BAND OF INTEREST
BAND OF INTEREST
BAND OF INTEREST
Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency
Figure 23. Σ-Δ ADC, Quantization Noise
Figure 24. Σ-Δ ADC, Noise Shaping
Decimation
Rate
128×
256×
128×
256×
DIGITAL FILTER CUTOFF FREQUENCY
QUANTIZATION NOISE
NOISE SHAPING
Data State
Fully filtered
Fully filtered
Fully filtered
Fully filtered
f
f
f
ICLK
ICLK
ICLK
Computation
Delay
3.1 µs
4.65 µs
5.05 µs
7.57 µs
/2
/2
/2
ICLK
. This
Rev. A | Page 15 of 32
Filter Delay
174 µs
346.8 µs
283.2 µs
564.5 µs
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 25) while also
reducing the data rate from f
f
decimation rate used.
The AD7765 employs three FIR filters in series. By using
different combinations of decimation ratios, data can be
obtained from the AD7765 at three data rates.
The first filter receives data from the modulator at ICLK
where it is decimated 4× to output data at (ICLK/4)
second filter allows a choice of decimation rates: 16× or 32×.
The third filter has a fixed decimation rate of 2×. Table 6 shows
some characteristics of the digital filtering where ICLK =
MCLK/2. The group delay of the filter is defined to be the
delay to the center of the impulse response and is equal to the
computation plus the filter delays. The delay until valid data is
available (the FILTER-SETTLE status bit is set) is approximately
twice the filter delay plus the computation delay. This is listed in
terms of MCLK periods in Table 6.
ICLK
/128 or less at the output of the filter, depending on the
–100
–120
–140
–160
–20
–40
–60
–80
0
Figure 26. Filter Frequency Response (156.25 kHz ODR)
0
SYNC
FILTER-SETTLE
14217 × t
27895 × t
14217 × t
27895 × t
to
50
MCLK
MCLK
MCLK
MCLK
100
FREQUENCY (kHz)
ICLK
Pass-Band
Bandwidth
62.5 kHz
31.25 kHz
38.4 kHz
19.2 kHz
at the input of the filter to
150
PASS-BAND RIPPLE = 0.1dB
–0.1dB FREQUENCY = 125.1kHz
–3dB FREQUENCY = 128kHz
STOP BAND = 156.25kHz
200
Output Data Rate
(ODR)
156.25 kHz
78.125 kHz
96 kHz
48 kHz
250
AD7765
MHz
300
MHz
. The