AD9211 Analog Devices, AD9211 Datasheet
AD9211
Specifications of AD9211
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AD9211 Summary of contents
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... LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). ...
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... Theory of Operation ...................................................................... 19 Analog Input and Voltage Reference ....................................... 19 Clock Input Considerations...................................................... 20 Power Dissipation and Power-Down Mode ........................... 21 Digital Outputs ........................................................................... 21 Timing ......................................................................................... 22 RBIAS........................................................................................... 22 AD9211 Configuration Using the SPI ..................................... 22 Hardware Interface..................................................................... 23 Configuration Without the SPI ................................................ 23 Memory Map .................................................................................. 25 Reading the Memory Map Table.............................................. 25 Reserved Locations .................................................................... 25 Default Values ............................................................................. 25 Logic Levels ...
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... MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9211. 5 Double data rate mode; user-programmable feature. See the Memory Map section. = +85° −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. ...
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... Full −75 25°C −77 −72 Full −72 25°C −86 −82 Full −82 25°C −83 −81 Full −81 25°C −81 −74 Full −74 25°C −78 25°C −86 25°C 700 Rev Page AD9211-250 AD9211-300 Typ Max Min Typ 59.4 58.6 59.2 57.5 59.3 58.5 59.1 57.0 59.0 58.3 58.7 57.0 59.4 58.6 59.1 57.3 59.2 58.4 59.0 57.0 59.0 58.2 58.8 56.7 9.7 9.7 9.7 9.7 9.7 9.6 − ...
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... AVDD 3.6 1.2 3.6 0.8 0 0.8 +10 −10 +10 +10 −10 + 0.8 × VDD 0.2 × 0.2 × AVDD AVDD 0 0 −60 − 454 247 454 1.375 1.125 1.375 AD9211 Unit μA μA kΩ μA μA μA μ ...
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... Full CPD Data to DCO Skew (t ) Full SKEW Latency Full Aperture Uncertainty (Jitter 25° See Figure 2. 2 See Figure 3. = +85° −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. MAX IN AD9211-200 AD9211-250 Min Typ Max Min 200 250 40 2.25 2.5 1.8 2.25 2.5 1.8 3.0 0.2 0.2 3.9 −0.3 +0.1 +0.5 − ...
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... Rev Page – – – – – – – – – – – – – 4 AD9211 – – 3 ...
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... AD9211 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0− through D9+/D9− to DRGND DCO to DRGND OR to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND SDIO/DCS to DGND PWDN to AGND CSB to AGND SCLK/DFS to AGND ...
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... D5+ 12 PIN 0 (EXPOSED PADDLE) = AGND D6– 13 D6+ 14 DNC = DO NOT CONNECT Figure 4. AD9211 Single Data Rate Mode Pin Configuration Description 1.8 V Analog Supply. 1.8 V Digital Output Supply. Analog Ground. Digital Output Ground. Analog Input—True. Analog Input—Complement. Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN− ...
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... AD9211 Pin No. Mnemonic 11 D5− 12 D5+ 13 D6− 14 D6+ 15 D7− 16 D7+ 17 D8− 18 D8+ 19 D9− 20 D9+ 21 OR− 22 OR+ 1 AGND and DRGND should be tied to a common quiet ground plane. Description D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. ...
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... DNC 12 PIN 0 (EXPOSED PADDLE) = AGND DNC 13 DNC 14 DNC = DO NOT CONNECT Figure 5. AD9211 Double Data Rate Pin Configuration Description 1.8 V Analog Supply. 1.8 V Digital Output Supply. Analog Ground. Digital Output Ground. Analog Input—True. Analog Input—Complement. Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN− ...
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... AD9211 Pin No. Mnemonic 9 OR− 20, 51, 52 DNC 21 DNC/(OR−) 22 DNC/(OR+) 1 AGND and DRGND should be tied to a common quiet ground plane. Description D6 Complement Output Bit. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) D6 True Output Bit. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.) Do Not Connect ...
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... AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, T otherwise noted. 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 6. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz 0 200MSPS 70.3MHz @ –1.0dBFS SNR: 59.3dB –20 ENOB: 9.7BITS SFDR: –77dBc –40 –60 –80 –100 –120 ...
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... SNR: 59.4dB ENOB: 9.7BITS SFDR: 86dBc 93.75 125.00 Figure 16. AD9211-250 Single-Tone SNR/SFDR vs. Input Frequency (f 93.75 125.00 Figure 17. AD9211-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz Rev Page 250MSPS 170.3MHz @ –1.0dBFS SNR: 59.0dB –20 ENOB: 9.7BITS SFDR: –79dBc – ...
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... Figure 21. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 70.3 MHz 0 –20 –40 –60 –80 –100 –120 768 1024 0 Figure 22. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 170.3 MHz 125 150 0 Figure 23. AD9211-300 Single-Tone SNR/SFDR vs. Input Frequency (f Rev ...
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... SFDR (dBFS SNR (dBFS SFDR (dB –90 –80 –70 –60 –50 –40 AMPLITUDE (dBFS) Figure 24. AD9211-300 SNR/SFDR vs. Input Amplitude; 300 MSPS, 170.3 MHz 0.25 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 0 256 512 OUTPUT CODE Figure 25. AD9211-300 INL; 300 MSPS 0 –20 – ...
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... Figure 30. SNR/SFDR vs. Common-Mode Voltage; 300 MSPS, 70.3 MHz @ −1 dBFS 2.5 2.0 1.5 1.0 0.5 0 –0.5 1 –60 –40 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 –40 –30 –20 –10 Rev Page AD9211 – 100 120 TEMPERATURE (°C) Figure 31. Gain vs. Temperature TEMPERATURE (°C) Figure 32. Offset vs. Temperature ...
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... AD9211 EQUIVALENT CIRCUITS AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 33. Clock Inputs AVDD VIN+ BUF 2kΩ BUF AVDD 2kΩ VIN– BUF Figure 34. Analog Inputs (V CML 1kΩ SCLK/DFS RESET 30kΩ PWDN Figure 35. Equivalent SCLK/DFS, RESET, PWDN Input Circuit CLK– ...
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... During power-down, the output buffers go into a high impedance state. ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9211 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical ...
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... This allows a wide range of clock input duty cycles without affecting the performance of the AD9211. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, 0.1µ ...
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... Figure 47). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9211. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...
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... Figure 2 and Figure 3 for more information. Output Data Rate and Pinout Configuration The output data of the AD9211 can be configured to drive 10 pairs of LVDS outputs at the same rate as the input clock signal (single data rate, or SDR, mode), or five pairs of LVDS outputs at 2× ...
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... The pins described in Table 9 comprise the physical interface between the user’s programming device and the serial port of the AD9211. All serial pins are inputs with an open-drain configuration and should be tied to an external pull-up or pull- down resistor (suggested value of 10 kΩ). ...
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... AD9211 Table 11. Serial Timing Definitions Parameter Timing (minimum, ns CLK EN_SDIO t 5 DIS_SDIO Table 12. Output Data Format Input (V) Condition (V) VIN+ − VIN− < 0.62 VIN+ − VIN− = 0.62 VIN+ − VIN− ...
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... Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” AN-877 Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset 8-bit chip ID, Bits[7:0] AD9211 = 0x06 0 Speed grade 300 MSPS 01 = 250 MSPS 10 = 200 MSPS Rev Page AD9211 Default ...
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... AD9211 Addr. Bit 7 (Hex) Parameter Name (MSB) Bit 6 ADC Functions 08 modes clock test_io OF ain_config output_mode 0 15 output_adjust output_phase Output 0 clock polarity 1 = inverted 0 = normal (default) Bit 5 Bit 4 Bit 3 Bit 2 PWDN Internal power-down mode full 000 = normal (power-up, ...
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... Input voltage range setting: 10000 = 0.98 V 10001 = 1.00 V 10010 = 1.02 V 10011 = 1.04 V … 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V … 01110 = 1.48 V 01111 = 1.50 V Rev Page AD9211 Default Bit 0 Value Default Notes/ Bit 1 (LSB) (Hex) Comments 00000001 position enable: (DDR mode ...
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... Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board with AD9211BCPZ-200 LVDS Evaluation Board with AD9211BCPZ-250 LVDS Evaluation Board with AD9211BCPZ-300 D06041-0-5/07(0) Rev Page ...