AD7690 Analog Devices, AD7690 Datasheet - Page 22

• Manufacturer Part Number: AD7690
• Manufacturer: Analog Devices

Specifications of AD7690

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 400kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7690
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7690s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7690s is shown
in Figure 44, and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
A
B
C
C
SDI
CONVERSION
t
t
DSDOSDI
t
SSCKCNV
t
CONV
DSDOSDI
AD7690
t
EN
CNV
SCK
A
SDO
t
t
t
SSDISCK
HSDO
DSDO
1
D
D
D
C
A
B
2
17 D
17 D
17 D
Figure 45. Chain Mode with Busy Indicator Serial Interface Timing
Figure 44. Chain Mode with Busy Indicator Connection Diagram
C
A
B
3
16 D
16 D
16 D
t
SDI
SCKH
C
t
A
B
4
HSDISCK
15
15
15
AD7690
CNV
SCK
B
17
t
SCK
Rev. B | Page 22 of 24
D
D
D
18
SDO
C
B
A
1
1
1
t
SCKL
D
D
D
19
C
B
A
0
0 D
0
D
ACQUISITION
20
B
A
17 D
17 D
t
CYC
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7690 ADC labeled C in Figure 44) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7690 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N + 1 clocks are required to
read back the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7690s in the
chain, provided the digital host has an acceptable hold time.
21
B
A
SDI
t
16
16
ACQ
AD7690
CNV
SCK
35
C
D
D
36
B
A
SDO
1
1
D
D
37
B
A
0 D
0
38
A
17
D
39
A
16
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
53
t
DSDOSDI
D
54
t
A
DSDOSDI
t
1
DSDOSDI
D
55
A
0