AD7322 Analog Devices, AD7322 Datasheet - Page 31

• Manufacturer Part Number: AD7322
• Description: Software Selectable True Bipolar Input, 2-Channel, 12-Bit Plus Sign ADC
• Manufacturer: Analog Devices

Specifications of AD7322

• Resolution (bits): 13bit
• # Chan: 2
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 2.5V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

MICROPROCESSOR INTERFACING
The serial interface on the AD7322 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7322 with some common micro-
controller and DSP serial interface protocols.
AD7322 TO ADSP-21xx
The ADSP-21xx family of DSPs interface directly to the AD7322
without requiring glue logic. The V
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial
interface. The SPORT0 on the ADSP-21xx should be configured
as shown in Table 14.
Table 14. SPORT0 Control Register Setup
Setting
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 51. The ADSP-21xx
has TFS0 and RFS0 tied together. TFS0 is set as an output, and
RFS0 is set as an input. The DSP operates in alternative framing
mode, and the SPORT0 control register is set up as described in
Table 14. The frame synchronization signal generated on the
TFS is tied to CS and, as with all signal processing applications,
requires equidistant sampling. However, as in this example, the
timer interrupt is used to control the sampling rate of the ADC
and under certain conditions equidistant sampling cannot be
achieved.
The timer registers are loaded with a value that provides an
interrupt at the required sampling interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
V
DRIVE
AD7322
Figure 51. Interfacing the AD7322 to the ADSP-21xx
DOUT
SCLK
1
DIN
CS
Description
Alternative framing
Active low frame signal
Right justify data
16-bit data word
Internal serial clock
Frame every word
Internal receive frame sync
Internal transmit frame sync
DRIVE
pin of the AD7322 takes
SCLK0
TFS0
RFS0
DT0
DR0
ADSP-21xx
V
DD
1
Rev. A | Page 31 of 36
The frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given (AX0 = TX0),
the state of the serial clock is checked. The DSP waits until the
SCLK goes high, low, and then high again before starting the
transmission. If the timer and SCLK are chosen so that the
instruction to transmit occurs on or near the rising edge of
SCLK, data can be transmitted either immediately or at the next
clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
an SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation leads
to nonequidistant sampling because the transmit instruction occurs
on an SCLK edge. If the number of SCLKs between interrupts is
an integer of N, equidistant sampling is implemented by the DSP.
AD7322 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interface directly to the
AD7322 without requiring glue logic, as shown in Figure 52.
The SPORT0 Receive Configuration 1 register should be set up
as outlined in Table 15.
Table 15. SPORT0 Receive Configuration 1 Register
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
V
DRIVE
AD7322
Figure 52. Interfacing the AD7322 to the ADSP-BF53x
DOUT
SCLK
1
DIN
CS
Description
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
Receive MSB first
Zero fill
Internal receive clock
Receive enable
16-bit data-word
Transmit and receive frame sync
RSCLK0
RFS0
DT0
DR0
ADSP-BF53x
V
DD
AD7322
1