AD7322 Analog Devices, AD7322 Datasheet - Page 6

• Manufacturer Part Number: AD7322
• Description: Software Selectable True Bipolar Input, 2-Channel, 12-Bit Plus Sign ADC
• Manufacturer: Analog Devices

Specifications of AD7322

• Resolution (bits): 13bit
• # Chan: 2
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 2.5V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7322
TIMING SPECIFICATIONS
Unless otherwise noted, V
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
10
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t
REF
2
= 2.5 V to 3.0 V internal/external, T
V
50
14
16 × t
75
12
25
45
26
57
0.4 × t
0.4 × t
13
40
10
4
2
750
500
25
DOUT
SCLK
CC
DIN
CS
< 4.75 V
THREE-
SCLK
STATE
SCLK
SCLK
Limit at T
WRITE
ZERO
DD
t
2
= 12 V to 16.5 V, V
1
V
50
20
16 × t
60
5
20
35
14
43
0.4 × t
0.4 × t
8
22
9
4
2
750
500
25
t
ZERO
3
CC
IDENTIFICATION BIT
t
ZERO
= 4.75 V to 5.25 V
9
MIN
SCLK
SCLK
SCLK
2
, T
ADD0
MAX
REG
A
SEL
= T
3
SIGN
MAX
MSB
SS
to T
= −12 V to −16.5 V, V
4
DB11
Figure 2. Serial Interface Timing Diagram
t
MIN
t
6
4
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
μs typ
t
CONVERT
t
.
10
1
5
t
DB10
7
Rev. A | Page 6 of 36
Description
t
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power up from autostandby
Power up from full shutdown/autoshutdown mode, internal reference
Power up from full shutdown/autoshutdown mode, external reference
SCLK
2
at 20 ns, the mark space ratio must be limited to 50:50.
CC
13
= 1/f
DB2
= 2.7 V to 5.25 V, V
SCLK
14
t
5
DB1
LSB
15
DB0
DON’T
CARE
16
DRIVE
THREE-STATE
t
8
= 2.7 V to 5.25, V
DRIVE
t
QUIET
) and timed from a voltage level of 1.6 V.
t
1
DRIVE
≤ V
CC
,