AD7687 Analog Devices, AD7687 Datasheet - Page 23

• Manufacturer Part Number: AD7687
• Manufacturer: Analog Devices

Specifications of AD7687

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

Data Sheet
ACQUISITION
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7687s
on a 3-wire serial interface while providing a BUSY indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7687s is shown
in Figure 45 and the corresponding timing is given in Figure 46.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
SDI
A
B
C
C
AD7687
CONVERSION
t
CNV
SCK
t
DSDOSDI
t
SSCKCNV
t
A
CONV
DSDOSDI
t
EN
SDO
t
t
t
SSDISCK
HSDO
DSDO
1
D
D
D
C
A
B
2
15 D
15 D
15 D
Figure 46. Chain Mode with BUSY Indicator Serial Interface Timing
C
Figure 45. Chain Mode with BUSY Indicator Connection Diagram
A
B
3
14 D
14 D
14 D
SDI
t
SCKH
C
A
B
4
t
HSDISC
13
13
13
AD7687
CNV
SCK
B
15
t
SCK
SDO
D
D
D
16
Rev. B | Page 23 of 28
C
A
B
1
1
1
t
SCKL
D
D
D
17
C
B
A
0
0
0 D
D
ACQUISITION
18
B
A
15 D
15 D
t
CYC
Figure 45) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7687 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N +
1 clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate and
consequently more AD7687s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to eight AD7687s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
19
B
A
SDI
t
14
14
ACQ
AD7687
31
CNV
SCK
C
D
D
32
B
A
1
1
SDO
D
D
33
B
A
0 D
0
34
A
15
D
35
A
14
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
47
t
DSDOSDI
D
48
t
DSDOSDI
A
t
1
DSDOSDI
D
49
A
0
AD7687