AD7994 Analog Devices, AD7994 Datasheet

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AD7994

Manufacturer Part Number
AD7994
Description
4 Channel, 12-Bit ADC with I2C Compatible Interface in 16-Lead TSSOP
Manufacturer
Analog Devices
Datasheet

Specifications of AD7994

Resolution (bits)
12bit
# Chan
4
Sample Rate
188kSPS
Interface
I²C/Ser 2-Wire,Ser
Analog Input Type
SE-Uni
Ain Range
Uni (Vref)
Adc Architecture
SAR
Pkg Type
SOP

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FEATURES
10- and 12-bit ADC with fast conversion time: 2 µs typ
4 single-ended analog input channels
Specified for V
Low power consumption
Fast throughput rate: 188 kSPS
Temperature range:−40°C to +125°C
Sequencer operation
Automatic cycle interval mode
I
I
Out-of-range indicator/alert function
Pin-selectable addressing via AS
Shutdown mode: 1 µA max
16-lead TSSOP package
See
GENERAL DESCRIPTION
The AD7993/AD7994 are 4-channel, 10- and 12-bit, low power,
successive approximation ADCs with an I
face. The parts operate from a single 2.7 V to 5.5 V power
supply and feature a 2 µs conversion time. The parts contain a
4-channel multiplexer and track-and-hold amplifier that can
handle input frequencies up to 11 MHz.
The AD7993/AD7994 provide a 2-wire serial interface that is
compatible with I
AD7993-0/AD7994-0 and AD7993-1/AD7994-1, and each
version allows for at least two different I
interface on the AD7993-0/AD7994-0 supports standard and
fast I
AD7994-1 supports standard, fast, and high speed I
modes.
The AD7993/AD7994 normally remain in a shutdown state
while not converting, and power up only for conversions. The
conversion process can be controlled using the CONVST pin,
by a command mode where conversions occur across I
operations, or an automatic conversion interval mode selected
through software control.
The AD7993/AD7994 require an external reference that should
be applied to the REF
V
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
2
2
C®-compatible serial interface
C interface supports standard, fast, and high speed modes
DD
equivalent devices, respectively.
. This allows the widest dynamic input range to the ADC.
AD7998
2
C interface modes. The I
and
DD
2
AD7992
of 2.7 V to 5.5 V
C interfaces. Each part comes in two versions,
IN
pin and can be in the range of 1.2 V to
for 8-channel and 2-channel
2
C interface on the AD7993-1/
2
C addresses. The I
2
C-compatible inter-
2
C interface
4-Channel, 10- and 12-Bit ADCs with I
2
C write
Compatible Interface in 16-Lead TSSOP
2
C
On-chip limit registers can be programmed with high and low
limits for the conversion result, and an open-drain, out-of-
range indicator output (ALERT) becomes active when the
programmed high or low limits are violated by the conversion
result. This output can be used as an interrupt.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
V
V
V
V
IN
IN
IN
AS
IN
3
1
2
4
2 µs conversion time with low power consumption.
I
addresses. Two AD7993/AD7994 versions allow five
AD7993/AD7994 devices to be connected to the same
serial bus.
The parts feature automatic shutdown while not converting
to maximize power efficiency. Current consumption is
1 µA max when in shutdown mode.
Reference can be driven up to the power supply.
Out-of-range indicator that can be software disabled or
enabled.
One-shot and automatic conversion rates.
Registers can store minimum and maximum conversion
results.
2
C-compatible serial interface with pin-selectable
REGISTER CH1–CH4
REGISTER CH1–CH4
AGND
REGISTER CH1–CH4
AD7993/AD7994
DATA
MUX
DATA
HYSTERESIS
I/P
V
FUNCTIONAL BLOCK DIAGRAM
DD
HIGH
LOW
T/H
LIMIT
LIMIT
© 2004 Analog Devices, Inc. All rights reserved.
AGND
APPROXIMATION
SUCCESSIVE
10-/12-BIT
Figure 1.
I
ADC
2
C INTERFACE
REF
AD7993/AD7994
IN
CONFIGURATION
ALERT STATUS
CYCLE TIMER
CONVERSION
REGISTER
REGISTER
REGISTER
REGISTER
RESULT
OSCILLATOR
CONTROL
CONVST
LOGIC
www.analog.com
SCL
SDA
ALERT/
BUSY
2
C-

Related parts for AD7994

AD7994 Summary of contents

Page 1

... AD7992 for 8-channel and 2-channel equivalent devices, respectively. GENERAL DESCRIPTION The AD7993/AD7994 are 4-channel, 10- and 12-bit, low power, successive approximation ADCs with an I face. The parts operate from a single 2 5.5 V power supply and feature a 2 µs conversion time. The parts contain a 4-channel multiplexer and track-and-hold amplifier that can handle input frequencies MHz ...

Page 2

... Writing Two Bytes of Data to a Limit or Hysteresis Register ........................................................................................ 24 Reading Data from the AD7993/AD7994................................... 26 Alert/Busy Pin................................................................................. 27 SMBus Alert ................................................................................ 27 Busy .............................................................................................. 27 Placing the AD7993-1/AD7994-1 into High Speed Mode ... 27 The Address Select (AS) Pin ..................................................... 27 Modes of Operation ....................................................................... 28 Mode 1—Using the CONVST Pin ........................................... 28 Mode 2—Command Mode....................................................... 29 Mode 3—Automatic Cycle Interval Mode.............................. 30 Outline Dimensions ...

Page 3

... V min DD 0 max DD ±1 µA max 10 pF max 0.1 min DD Rev Page AD7993/AD7994 = 2 5.5 V; REF = 2.5 V; For the AD7993- 3.4 MHz, unless otherwise noted. SCL Test Conditions/Comments kHz sine wave for f IN SCL to 3.4 MHz kHz sine wave for f IN SCL ...

Page 4

... AD7993/AD7994 Parameter LOGIC INPUTS (CONVST) Input High Voltage, V INH Input Low Voltage, V INL Input Leakage Current Input Capacitance LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage Floating-State Leakage Current 3 Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Throughput Rate ...

Page 5

... AD7994 SPECIFICATIONS Temperature range for B version is −40°C to +125°C. Unless otherwise noted, V all specifications apply for 400 kHz. For the AD7994-1, all specs apply for f SCL MIN MAX. Table 2. Parameter 1 DYNAMIC PERFORMANCE 2 Signal-to-Noise + Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR) ...

Page 6

... AD7993/AD7994 Parameter LOGIC INPUTS (CONVST) Input High Voltage, V INH Input Low Voltage, V INL Input Leakage Current Input Capacitance LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage Floating-State Leakage Current 3 Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Throughput Rate ...

Page 7

... Guaranteed by initial characterization. All values measured with input filtering enabled and tf measured between 0.3 V and 0 High speed mode timing specifications apply to the AD7993-1/AD7994-1 only. Standard and fast mode timing specifications apply to both the AD7993-0/AD7994-0 and the AD7993-1/AD7994-1. See Figure 2. Unless otherwise noted 2 5.5 V; REF DD Table 3 ...

Page 8

... A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. 2 For 3 V supplies, the maximum hold time with SCL SDA START CONDITION P = STOP CONDITION AD7993/AD7994 Limit MIN MAX Min Max Unit 300 0.1 C 300 160 ...

Page 9

... Exposure to absolute DD −0 maximum rating conditions for extended periods may affect −0 0.3 V device reliability ±10 mA −40°C to +125°C −65°C to +150° 150°C 150.4°C/W 27.6°C/W 240(+0/-5)°C 260(+0)°C 1.5 kV Rev Page AD7993/AD7994 ...

Page 10

... GND AD7993 AD7993-x Float AD7994-0 GND AD7994-0 V AD7994-1 GND AD7994-1 V AD7994-x Float the AS pin is left floating on any of the AD7993/AD7994 parts, the device address is 010 0000. AGND AGND 1 16 AGND SCL 2 15 AD7993/ AGND SDA 3 14 AD7994 ALERT/BUSY AGND 4 13 ...

Page 11

... The AD7993/AD7994 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually dis- ...

Page 12

... AD7993/AD7994 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –100 –120 FREQUENCY (kHz) Figure 4. AD7994 Dynamic Performance with 5 V Supply and 2.5 V Reference, 121 kSPS, Mode 1 –10 –30 –50 –70 –90 –110 FREQUENCY (kHz) Figure 5. AD7993 Dynamic Performance with 5 V Supply and 2 ...

Page 13

... V, Mode 1, 3.4 MHz f DD 1.0 0.8 0.6 0.4 POSITIVE INL 0.2 0 –0.2 NEGATIVE INL –0.4 -0.6 –0.8 –1.0 1.2 1.7 2.2 2.7 3.2 3.7 REFERENCE VOLTAGE (V) Figure 12. AD7994 Change in INL vs. Reference Voltage V Mode 1, 121 kSPS 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 -0.6 –0.8 –1.0 3500 4000 1.2 , 121 kSPS Figure 13. AD7994 Change in DNL vs. Reference Voltage V SCL 0.0007 0.0006 0.0005 0.0004 ...

Page 14

... TEMPERATURE = +85°C 1.8 TEMPERATURE = +25°C TEMPERATURE = –40°C 1.6 TEMPERATURE = +85°C TEMPERATURE = +25°C MODE 2 - 147kSPS 1.4 TEMPERATURE = –40°C 1.2 1.0 MODE 1 - 121kSPS 0.8 0.6 0.4 0.2 0 2.7 3.2 3.7 4.2 SUPPLY VOLTAGE (V) Figure 16. AD7994 Average Supply Current vs. Supply Voltage for Various Temperatures 12.0 11.8 11.6 11.4 11.2 11.0 10.8 10.6 10.4 4.7 5.2 Rev Page ENOB V DD ENOB SINAD V DD SINAD ...

Page 15

... SW1 AGND ADC Transfer Function The output coding of the AD7993/AD7994 is straight binary. The designed code transitions occur at successive integer LSB values—that is, 1 LSB, 2 LSB, and so on. The LSB size is REF /1024 for the AD7993 and REF IN Figure 20 shows the ideal transfer characteristic for the AD7993/AD7994 ...

Page 16

... AD7993/AD7994 TYPICAL CONNECTION DIAGRAM Figure 22 shows the typical connection diagram for the AD7993/ AD7994. In Figure 22 the address select pin (AS) is tied to V however, AS can also be tied to AGND or left floating, allowing the user to select up to five AD7993/AD7994 devices on the same serial bus. An external reference must be applied to the AD7993/AD7994 ...

Page 17

... INPUT FREQUENCY (kHz) Figure 23. THD vs. Analog Input Frequency for Various Supply Voltages, F –40 –50 –60 –70 –80 –90 –100 10 INPUT FREQUENCY (kHz) Figure 24. THD vs. Analog Input Frequency for Various Source Impedances for V Rev Page AD7993/AD7994 ...

Page 18

... LSBs are used as pointer bits to store an address that points to one of the AD7993/AD7994’s data registers. The 4 MSBs are used as command bits when operating in Mode 2 (see the Modes of Operation section). The first byte following each write address ...

Page 19

... CONFIGURATION REGISTER The configuration register is an 8-bit read/write register that is used to set the operating modes of the AD7993/AD7994. The bit functions are outlined in Table 9. A single-byte write is necessary when writing to the configuration register. Table 9. Configuration Register Bit Function Descriptions and Default Settings at Power-Up ...

Page 20

... Each pair of limit registers has one associated hysteresis register. All 12 registers are 16 bits wide; only the 12 LSBs of the registers are used for the AD7993/AD7994. For the AD7993, the 2 LSBs, D1 and D0, should contain 0s. On power-up, the contents of the DATA ...

Page 21

... CH1, the address of which is shown in Table 8. On power-up, the hysteresis registers contain a value of 8 LSB for the AD7994 and 2 LSB for the AD7993 different hysteresis value is required, that value must be written to the hysteresis register for the channel in question ...

Page 22

... On power-up, the cycle timer register contains all 0s, thus disabling automatic cycle operation of the AD7993/AD7994. To enable automatic cycle mode, the user must write to the cycle timer register, selecting the required conversion interval. Table 24 shows the structure of the cycle timer register while Table 25 shows how the bits in this register are decoded to provide various automatic sampling intervals ...

Page 23

... Table 6). By giving DD different addresses for the two versions five AD7993/ AD7994 devices can be connected to a single serial bus, or the addresses can be set to avoid conflicts with other devices on the bus. See Table 6. The serial bus protocol operates as follows: ...

Page 24

... See Figure 28. If the master is write addressing the AD7993/AD7994, it can write to more than one register. After the first write operation has completed for the first data register in the next byte, the master writes to the address pointer byte to select the next data register for a write operation ...

Page 25

... R ACK. BY AD7993/AD7994 FRAME 1 ADDRESS POINTER REGISTER D11 D10 ACK. BY AD7993/AD7994 LEAST SIGNIFICANT DATA BYTE Figure 28. Two-Byte Write Sequence Rev Page AD7993/AD7994 ACK. BY AD7993/AD7994 FRAME D1/0 D0/0 ACK. BY STOP BY AD7993/AD7994 MASTER ...

Page 26

... When reading data back from a register on the AD7993 or the AD7994, for example the conversion result register, if more than two read bytes are supplied, the same or new data is read from the AD7993/AD7994 without the need to readdress the device. ...

Page 27

... All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices all return to fast mode. THE ADDRESS SELECT (AS) PIN The address select pin on the AD7993/AD7994 is used to set 2 the I can be tied to V should be made as close as possible to the AS pin; avoid having long tracks introducing extra capacitance on the pin ...

Page 28

... I C interface. On the rising edge of CONVST , the AD7993/AD7994 begin to power up (see Point A in Figure 32). The power-up time from shutdown mode for the AD7993/AD7994 is approximately 1 µs; the CONVST signal must remain high for 1 µs for the part to power up fully ...

Page 29

... MHz SCL, the conversion may not be complete before the master tries to read the conversion result. If this is the case, the AD7994-1/AD7993-1 hold the SCL line low during the ACK clock after the read address until the con- version is complete. When the conversion is complete, the AD7994-1/AD7993-1 release the SCL line and the master can then read the conversion result ...

Page 30

... An automatic conversion cycle can be selected and enabled by writing a value to the cycle timer register. A conversion cycle interval can be set up on the AD7993/AD7994 by programming the relevant bits in the 8-bit cycle timer register, as decoded in Table 25. Only the 3 LSB are used; the 5 MSB should contain 0s. ...

Page 31

... LSB ±0.5 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB 2 C interface modes. The AD7993-1/AD7994-1 support standard, fast, and high speed I Number of Input Channels Rev Page AD7993/AD7994 0.75 0.60 0.45 Package Option ...

Page 32

... AD7993/AD7994 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03472– ...

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