AD9216 Analog Devices, AD9216 Datasheet - Page 22

• Manufacturer Part Number: AD9216
• Description: 10-Bit, 65/80/105 MSPS Dual A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9216

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 105MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,(Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9216
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9216 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels asyn-
chronously may degrade performance significantly. In some
applications, it is desirable to skew the clock timing of adjacent
channels. The AD9216’s separate clock inputs allow for clock
timing skew (typically ±1 ns) between the channels without
significant performance degradation.
The AD9216 contains two clock duty cycle stabilizers, one for
each converter, that retime the nonsampling edge, providing an
internal clock with a nominal 50% duty cycle. Faster input clock
rates, where it becomes difficult to maintain 50% duty cycles,
can benefit from using DCS, as a wide range of input clock duty
cycles can be accommodated. Maintaining a 50% duty cycle
clock is particularly important in high speed applications, when
proper track-and-hold times for the converter are required to
maintain high performance. The DCS can be enabled by tying
the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 µs to 3 µs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated by
In the equation, the rms aperture jitter, t
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification. Under-
sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aper-
ture jitter may affect the dynamic range of the AD9216, it
is important to minimize input clock jitter. The clock input
circuitry should use stable references; for example, use analog
power and ground planes to generate the valid high and low
digital levels for the AD9216 clock input. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal-controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
SNR degradation = 2 × log 10[1/2 × p × f
INPUT
) due only to aperture jitter (t
J
, represents the root-
INPUT
× t
J
) can be
J
]
Rev. A | Page 22 of 40
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9216 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers
and the load on each output bit. The digital drive current can
be calculated by
where N is the number of bits changing, and C
load on the digital pins that changed.
The analog circuitry is optimally biased, so each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at
low sample rates that increases with clock frequency.
Either channel of the AD9216 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
Time to go into or come out of standby mode is 5 cycles maxi-
mum when only one channel is being powered down. When both
channels are powered down, VREF goes to ground, resulting in a
wake-up time of ~7 ms dependent on decoupling capacitor
values.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 3 mW for the ADC.
If the clock inputs remain active while in total standby mode,
typical power dissipation of 10 mW results.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B
= HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time is directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down.
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
DIGITAL OUTPUTS
The AD9216 output drivers can interface directly with 3 V
logic families. Applications requiring the ADC to drive large
capacitive loads or large fanouts may require external buffers
or latches because large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
The data format can be selected for either offset binary or twos
complement. This is discussed in the Data Format section.
I
DRVDD
= V
DRVDD
× C
LOAD
× f
CLOCK
× N
LOAD
is the average