AD9481 Analog Devices, AD9481 Datasheet
AD9481
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AD9481 Summary of contents
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... The AD9481 is available in a Pb-free, 44-lead, surface-mount package (TQFP-44) specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. Superior linearity. A DNL of ±0.35 makes the AD9481 suitable for many instrumentation and measurement applications 2. Power-down mode. A power-down function may be exercised to bring total consumption down ...
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... Voltage Reference ....................................................................... 17 Clocking the AD9481................................................................. 19 DS Inputs ..................................................................................... 19 Digital Outputs ........................................................................... 20 Interleaving Two AD9481s........................................................ 20 REVISION HISTORY 10/04—Revision 0: Initial Version Data Clock Out........................................................................... 20 Power-Down Input..................................................................... 20 AD9481 Evaluation Board ............................................................ 21 Power Connector........................................................................ 21 Analog Inputs.............................................................................. 21 Gain.............................................................................................. 21 Optional Operational Amplifier............................................... 21 Clock ............................................................................................ 21 Optional Clock Buffer ............................................................... 21 DS ................................................................................................. 21 Optional XTAL ........................................................................... 22 Voltage Reference ....................................................................... 22 Data Outputs ...
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... Full V Full VI 1.6 Full VI 8.4 25°C V 25°C V Full IV 3.0 Full IV 3.0 Full VI Full VI 25°C V 25°C V 25°C V Rev Page AD9481 AD9481-250 Typ Max Unit 8 Bits Guaranteed ±0.35 0.85 LSB ±0.26 0.9 LSB 30 µV/°C 0.03 % FS/°C ±0.025 mV/°C 1.0 1.03 V 1.5 mA 100 µA 10 µ ...
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... IN Temp Test Level Full IV Full VI Full VI 25°C V Full IV Full IV Full VI Full VI 25°C V 25°C V Full VI Full VI Full IV Rev Page AD9481-250 Min Typ Max 200 1.38 1.5 1.68 4.2 5.5 6.0 4 2.0 0.8 ±160 DRVDD − 0.05 0.05 Twos complement or binary Unit mV p-p V kΩ µA µA kΩ ...
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... Rev Page AD9481-250 Test Level Min Typ Max 44.5 45.7 V 45.9 I 44.4 45.7 V 7.5 I 7.2 7.5 V −64.8 I −64.8 −54 V −68 I −65.8 −56 V −64.8 I −64.8 −54 V −64.9 AD9481 Unit Bits Bits dBc dBc dBc dBc dBc dBc dBc ...
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... IV Full IV Full VI Full VI Full V Full V Full VI Full VI Full IV Full IV Full IV 25°C V 25°C V 25° − (Data to DCO skew). CYCLE Rev Page AD9481-250 Min Typ Max Unit 250 MSPS 20 MSPS 1 1 0.5 ns 0 5.4 ns 670 ps 360 ps 2.5 3.9 5.3 ns −0.5 +0 ...
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... DS+ DS– INTERLEAVED DATA OUT PORT A STATIC D7A TO D0A PORT B STATIC D7B TO D0B DCO+ DCO– N+1 N+7 8 CYCLES 1 HDS t SDS INVALID INVALID STATIC Figure 2. Timing Diagram Rev Page N+9 N+8 N+ INVALID N+1 t SKA t SKB t CPD AD9481 ...
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... AD9481 ABSOLUTE MAXIMUM RATINGS Thermal impedance (θ 46.4°C/W (4-layer PCB). JA Table 5. Min. Parameter Rating ELECTRICAL AVDD (With respect to AGND) −0.5 V DRVDD −0.5 V (With respect to DRGND) AGND (With respect to DRGND) −0.5 V Digital I/0 −0.5 V (With respect to DRGND) Analog Inputs −0.5 V (With respect to AGND) ...
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... V Analog Supply AGND Analog Ground VIN− Analog Input—Complement VIN+ Analog Input—True AGND Analog Ground AVDD 3.3 V Analog Supply S3 DCO Enable Select (Tie to AVDD for DCO Active) DS− Data Sync Complement (If Unused, Tie to DRVDD) DS+ Data Sync True (If Unused, Tie to DGND) AD9481 ...
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... Logic 1 state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. See timing implications of changing t in the Clocking the AD9481 section given clock rate, EH these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level (− ...
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... Out-of-Range Recovery Time This is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Rev Page AD9481 ...
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... AD9481 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3 25°C, A differential drive internal reference mode, unless otherwise noted –10 –20 –30 –40 –50 –60 –70 –80 – (MHz) Figure 4. FFT 250 MSPS 10.3 MHz @ −1 dBFS –10 –20 –30 – ...
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... Figure 14. SNR, SINAD vs. Clock Pulse-Width High, A 50.0 47.5 45.0 42.5 40.0 100 120 0.5 Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, A Rev Page AD9481 I AVDD I DRVDD 50 100 150 200 250 SAMPLE CLOCK (MSPS) and I vs. Clock Rate AVDD DRVDD LOAD MHz @ − ...
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... AD9481 2.0 1 EXTERNAL REFERENCE 1.0 0.5 0 –0.5 –1.0 INTERNAL REFERENCE –1.5 –2.0 –40 – TEMPERATURE (°C) Figure 16. Full-Scale Gain Error vs. Temperature 70.3 MHz @ −0.5 dBFS, 250 MSPS –40 – TEMPERATURE (°C) Figure 17. SINAD, SFDR vs. Temperature MHz @ −1 dBFS, 250 MSPS IN 0 ...
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... T _R CPD –0 –0.4 –40 – TEMPERATURE (°C) Figure 22. Propagation Delay Sensitivity vs. Temperature CPD 60 80 Rev Page AD9481 ...
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... AD9481 EQUIVALENT CIRCUITS 16.7kΩ 16.7kΩ 150Ω VIN+ 1.2pF 25kΩ Figure 23. Analog Inputs AVDD 12kΩ CLK+ 150Ω 10kΩ Figure 24. Clock Inputs 30kΩ S1 Figure 25. S1 Input AVDD 150Ω VIN– 1.2pF 25kΩ 12kΩ CLK– ...
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... AVDD VIN+ AD9481 VOLTAGE REFERENCE VIN– A stable and accurate 1.0 V reference is built into the AD9481. AGND Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure 32 shows the typical reference variation with temperature. Table 8 summarizes the available reference configurations. ...
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... VREF pin µF capacitor is also required (see the PCB layout for guidance). If the internal reference of the AD9481 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 34 depicts how the internal reference voltage is affected by loading ...
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... A/D output. Considerable care has been taken in the design of the CLOCK input of the AD9481, and the user is advised to give commensurate thought to the clock source. The AD9481 has an internal clock duty cycle stabilization ...
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... INTERLEAVING TWO AD9481s Duty Cycle Instrumentation applications may prefer to interleave (or ping- Stabilizer pong) two AD9481s to achieve twice the sample rate, or Disabled 500 MSPS. In these applications important to match the Enabled gain and offset of the two ADCs. Varying the reference voltage Enabled allows the gain of the ADCs to be adjusted ...
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... AD9481 EVALUATION BOARD The AD9481 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at an 80-pin output connector, P3, P23 ...
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... Vectron VCC6 family crystal is being used, populate R57 with a 10 Ω resistor. If using the XO-400 crystal, place jumper E21 or E22 to E23. VOLTAGE REFERENCE The AD9481 has an internal 1 V reference mode. The ADC uses OUT+ the internal 1 V reference as the default when sense is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the sense jumper to AVDD, by placing a jumper E3, and by placing a 0 Ω ...
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... SO-14 ADR510 SOT-23 VCC6PECL6 VCC6-QAB-250M000 AD9481 TQFP-44 MC100-LVEL16D S08NB ETC1-1-13 1-1 TX Capacitors 0402 Resistors 0603 Jumpers Rev Page AD9481 Value 0.1 µF 10 µF 10 µF Degrees Z5.531.3425.0 25.602.5453.0 TSW-140-08-L-D-RA 50 Ω 100 Ω 1 kΩ 130 Ω 510 Ω 82 Ω 00 Ω 10 kΩ 2 kΩ ...
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... AD9481 PCB SCHEMATICS D4B D5B D6B D7B GND DRGND S1 S1 PWDN PWDN 1 P1 AVDD AVDD 2 P2 AVDD AVDD 3 GND P3 AGND GND 4 VAMP P4 SENSE 1 P1 GND 2 P2 VDL 3 P3 GND 4 P4 DRVDD 1 GND P1 2 AVDD P2 3 GND P3 4 VCTRL P4 D3A D4A D5A ...
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... Figure 40. PCB Schematic ( Rev Page AD9481 05045-041 ...
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... AD9481 PCB LAYERS August 3, 2004 Figure 41. PCB Top-Side Silkscreen Figure 42. PCB Top-Side Copper Routing Figure 43. PCB Ground Layer Figure 44. PCB Split Power Plane Rev Page ...
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... Figure 45. PCB Bottom-Side Copper Routing Figure 46. PCB Bottom-Side Silkscreen Rev Page AD9481 ...
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... ORDERING GUIDE Model Temperature Range 1 AD9481BSUZ-250 –40°C to +85°C AD9481-PCB Pb-free part. 2 Evaluation board shipped with AD9481BSUZ-250 installed. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05045–0–10/04(0) 1.20 MAX 0.75 44 0.60 1 0.45 ...