AD9481 Analog Devices, AD9481 Datasheet - Page 21

• Manufacturer Part Number: AD9481
• Description: 8-Bit, 250 MSPS, 3.3 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9481

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,1 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD9481 EVALUATION BOARD
The AD9481 evaluation board offers an easy way to test the
device. It requires a clock source, an analog input signal, and a
3.3 V power supply. The clock source is buffered on the board to
provide the clocks for the ADC and a data-ready signal. The
digital outputs and output clocks are available at an 80-pin
output connector, P3, P23. (Note that P3, P23 are represented
schematically as two 40-pin connectors, and this connector is
implemented as one 80-pin connector on the PCB.) The board
has several different modes of operation and is shipped in the
following configuration:
•
•
POWER CONNECTOR
Power is supplied to the board via two detachable 4-pin power
strips.
Table 11. Power Connector
Terminal
VDL (3.3 V)
AVDD
DRVDD
VCTRL
Op amp, ext. ref
1
AVDD, DRVDD, VDL, and VCTRL are the minimum required power
connections.
Offset binary
Internal voltage reference
1
1
3.3 V
1
3.3 V
3.3 V
Comments
Output supply for external latches and data
ready clock buffer ~ 30 mA
Analog supply for ADC ~ 140 mA
Output supply for ADC ~ 30 mA
Supply for support clock circuitry ~ 60 mA
Optional supply for op amp and ADR510
reference
Rev. 0 | Page 21 of 28
ANALOG INPUTS
The evaluation board accepts a 700 mV p-p analog input signal
centered at ground at SMB Connector J3. This signal is
terminated to ground through 50 Ω by R22. The input can be
alternatively terminated at the T1 transformer secondary by
R21 and R28. T1 is a wideband RF transformer that provides
the single-ended-to-differential conversion, allowing the ADC
to be driven differentially, minimizing even-order harmonics.
An optional transformer, T4, can be placed if desired (remove
T1, as shown in Figure 39 and Figure 40).
The analog signal can be low-pass filtered by R21, C8 and R28,
C9 at the ADC input.
GAIN
Full scale is set by the sense jumper. This jumper applies a bias
to the SENSE pin to vary the full-scale range; the default
position is SENSE = ground, setting the full scale to 1 V p-p.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8351 op amp that can serve as a convenient solution for dc-
coupled applications. To use the AD8351 op amp, remove R29,
R31, and C3. Populate R12, R17, and R36 with 25 Ω resistors,
and populate C1, C21, C23, C31, C39, and C30 with 0.1 µF
capacitors. Populate R54, R10, and R11 with 10 Ω resistors, and
R34 and R32 with 1 kΩ resistors. Populate R15 with a 1.2 kΩ
resistor and R14 with a 100 Ω resistor. Populate R37 with a
10 kΩ resistor.
CLOCK
The clock input is terminated to ground through 50 Ω at SMA
Connector J1. The input is ac-coupled to a high speed
differential receiver (LVEL16) that provides the required low
jitter, fast edge rates needed for best performance. J1 input
should be > 0.5 V p-p. Power to the LVEL16 is set to VCTRL
(default) or AVDD by jumper placement at the device.
OPTIONAL CLOCK BUFFER
The PCB has been designed to accommodate the SNLVDS1 line
driver. The SNLVDS1 is used as a high speed LVDS-level
optional encode clock. To use this clock, please remove C2, C5,
and C6. Place 0.1 µF capacitors on C34, C35, and C26. Place a
10 Ω resistor on R48, and place a 100 Ω resistor on R6. Place a
0 Ω resistor on both R49 and R53. For best results using the line
driver, J1 input should be > 2.5 V p-p.
DS
The DS inputs are available on the PCB at J2 and J4. If driving
DS+ externally, place a 0 Ω resistor at C48 and remove R53.
AD9481