AD7653 Analog Devices, AD7653 Datasheet
AD7653
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AD7653 Summary of contents
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... Internal Reference. The AD7653 has an internal reference with a typical temperature drift of 7 ppm/°C. 3. Single-Supply Operation. The AD7653 operates from a single 5 V supply. In Impulse mode, its power dissipation decreases with the throughput. 4. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic ...
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... Changes to Voltage Reference Input section ........................... 18 Changes to Figure 31.................................................................. 20 Parallel Interface......................................................................... 20 Serial Interface ............................................................................ 20 Master Serial Interface ............................................................... 21 Slave Serial Interface .................................................................. 22 Microprocessor Interfacing....................................................... 24 Application Hints............................................................................ 25 Bipolar and Wider Input Ranges .............................................. 25 Layout .......................................................................................... 25 Evaluating the AD7653’s Performance .................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide........................................................................... 26 Page Rev Page ...
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... AVDD – 1.85 300 AD7653 Unit Bits µA µs kSPS ms µs kSPS µs kSPS 2 LSB Bits LSB LSB LSB ppm/° FSR ppm/°C LSB ...
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... AD7653 Parameter DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS 5 Data Format Pipeline Delay POWER SUPPLIES Specified Performance AVDD DVDD OVDD 8 Operating Current 9 AVDD AVDD 10 11 DVDD 11 OVDD Power Dissipation without REF Power Dissipation with REF 12 TEMPERATURE RANGE ...
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... See Table 0.75/1/1. pF; otherwise, the load maximum. L AD7653 Unit ns µs ns µ µ µ µ ...
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... AD7653 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum ...
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... ABSOLUTE MAXIMUM RATINGS Table 5. AD7653 Absolute Maximum Ratings Parameter TEMP ,REF, REFBUFIN, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD Digital Inputs 3 PDREF, PDBUF 4 Internal Power Dissipation 5 Internal Power Dissipation ...
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... EXT/ INT DI/O INVSYNC AGND 1 PIN 1 AVDD 2 IDENTIFIER NC 3 BYTESWAP 4 OB/2C 5 AD7653 WARP 6 TOP VIEW IMPULSE 7 (Not to Scale) SER/PAR D2/DIVSCLK0 11 D3/DIVSCLK1 CONNECT Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Description Analog Power Ground Pin ...
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... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external clock. Reset Input. When set to a logic HIGH, this pin resets the AD7653 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND. ...
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... AD7653 Pin No. Mnemonic Type 1 37 REF AI/O 38 REFGND AI 39 INGND TEMP AO 46 REFBUFIN AI/O 47 PDREF DI 48 PDBUF Analog Input; AI/O = Bidirectional Analog Analog Output Digital Input; DI/O = Bidirectional Digital Digital Output Power. Description Reference Input Voltage. On-chip reference output voltage. Reference Input Analog Ground. ...
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... Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Transient response is the time required for the AD7653 to achieve its rated accuracy after a full-scale step function is applied to its input. Overvoltage Recovery ...
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... AD7653 TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 –3 –4 0 16384 32768 CODE Figure 5. Integral Nonlinearity vs. Code 140000 114641 120000 112516 100000 80000 60000 40000 15906 20000 679 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 CODE IN HEX Figure 6. Histogram of 261,120 Conversions of a ...
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... AVDD, IMPULSE OVDD, ALL MODES PDREF = PDBUF = HIGH 1000 100 10000 100000 SAMPLE RATE (SPS) Figure 15. Operating Current vs. Sample Rate FULL SCALE ZERO ERROR – 105 –15 TEMPERATURE (°C) AD7653 105 125 02966-0-034 1000000 02966-0-036 125 02966-0-040 ...
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... AD7653 2.5020 2.5019 2.5018 2.5017 2.5016 2.5015 2.5014 2.5013 2.5012 2.5011 2.5010 2.5009 2.5008 –40 – TEMPERATURE (°C) Figure 17. Typical Reference Output Voltage vs. Temperature –30 –26 –22 –18 –14 –10 –6 –2 2 REFERENCE DRIFT (ppm/°C) Figure 18 ...
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... ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7653 can be operated from a single 5 V supply and can be interfaced to either digital logic housed in either a 48-lead LQFP or a 48-lead LFCSP that saves space and allows flexible configurations as either a serial or a parallel interface ...
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... AD7653 Transfer Functions Using the OB/ 2C digital input, the AD7653 offers two output codings: straight binary and twos complement. The LSB size is V /65536, which is about 38.15 µV. The AD7653’s ideal REF transfer characteristic is shown in Figure 21 1 LSB = V /65536 REF 111...111 111 ...
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... AD7653 can be driven directly. Large source impedances will significantly affect the ac performance, especially total harmonic distortion. Driver Amplifier Choice Although the AD7653 is easy to drive, the driver amplifier needs to meet the following requirements: • The driver amplifier and the AD7653 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’ ...
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... ANALOG INPUT (UNIPOLAR) Power Supply The AD7653 uses three power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. OVDD allows direct interface with any logic between 2.7 V and DVDD + 0 Figure 17 ...
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... PD, until the conversion is complete. CNVST operates independently of CS and Impulse mode, conversions can be automatically initiated. If CNVST is held LOW when BUSY is LOW, the AD7653 controls the acquisition phase and automatically initiates a new con- version. By keeping CNVST LOW, the AD7653 keeps the conversion process running by itself ...
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... D[15:8] or D[7:0]. SERIAL INTERFACE The AD7653 is configured to use the serial interface when SER/ PAR is held HIGH. The AD7653 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edges of the data clock ...
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... Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Usually, because the AD7653 is used with a fast throughput, the Master Read During Conversion mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions ...
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... Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) While the AD7653 is performing a bit decision important that voltage transients be avoided on digital input/output pins, or degradation of the conversion result could occur. This is particularly important during the second half of the conversion ...
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... Another advantage is the ability to read the data at any speed MHz, which accommodates both the slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7653 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters together. This feature is useful for reducing compo- nent count and wiring connections when desired, as, for instance, in isolated multiconverter applications ...
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... AD7653 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7653 acts as a slave device and data must be read after conversion. This mode also allows the daisy- chain feature. The convert command can be initiated in response to an internal timer interrupt ...
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... ADC to further INGND reduce low frequency ripple. REF The DVDD supply of the AD7653 can be a separate supply or can come from the analog supply AVDD or the digital interface REFGND supply OVDD. When the system digital supply is noisy or when ...
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... SEATING PLANE ORDERING GUIDE Model AD7653AST AD7653ASTRL AD7653ACP AD7653ACPRL 1 EVAL-AD7653CB 2 EVAL-CONTROL BRD2 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows control and communicate with all Analog Devices evaluation boards ending in the CB designators. ...
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... NOTES Rev Page AD7653 ...
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... AD7653 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02966–0–9/03(A) Rev Page ...