AD7653 Analog Devices, AD7653 Datasheet - Page 19

• Manufacturer Part Number: AD7653
• Manufacturer: Analog Devices

Specifications of AD7653

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

POWER DISSIPATION VS. THROUGHPUT
Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see F
mode used. In Impulse mode, the AD7653 automatically
reduces power consumption at the end of each conversion
phase. This makes the part ideal for very low power battery
applications. The digital interface and the reference remain
active even during the acquisition phase. To reduce operating
digital supply currents even further, digital inputs need to be
driven close to the power supply rails (i.e., DVDD or DGND),
and OVDD should not exceed DVDD by more than 0.3 V.
CONVERSION CONTROL
Figure 26
process. The AD7653 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD .
In Impulse mode, conversions can be automatically initiated. If
CNVST is held LOW when BUSY is LOW, the AD7653 controls
the acquisition phase and automatically initiates a new con-
version. By keeping CNVST LOW, the AD7653 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes low. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7653 can run slightly
faster than the guaranteed 666 kSPS limits in Impulse mode.
This feature does not exist in Warp and Normal modes.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
1000000
100000
10000
1000
100
10
shows the detailed timing diagrams of the conversion
10
Figure 25. Power Dissipation vs. Sampling Rate
igure 25
WARP MODE POWER
100
). This power savings depends on the
SAMPLE RATE (SPS)
1000
IMPULSE MODE POWER
PDREF = PDBUF = HIGH
10000
100000
02966-0-041
1000000
Rev. A | Page 19 of 28
The CNVST trace should be shielded with ground and a low
value serial resistor (i.e., 50
close to the output of the component that drives this line.
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock CNVST with a
high frequency, low jitter clock, as shown in
CS = RD = 0
CNVST
CNVST
MODE
BUSY
RESET
CNVST
BUSY
DATA
BUSY
DATA
BUS
Figure 28. Master Parallel Data Timing for Reading (Continuous Read)
ACQUIRE
t
t
3
5
t
3
Figure 26. Basic Conversion Timing
t
PREVIOUS CONVERSION DATA
CONVERT
1
Figure 27. RESET Timing
t
7
t
t
4
t
9
1
Ω
) termination should be added
t
2
t
6
t
10
ACQUIRE
t
t
8
4
t
8
Figure 22
t
11
AD7653
.
NEW DATA
CONVERT
02966-0-011
02966-0-012
02966-0-011