AD7928 Analog Devices, AD7928 Datasheet - Page 16

• Manufacturer Part Number: AD7928
• Description: 8-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7928

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

AD7908/AD7918/AD7928
Table 9. Power Mode Selection
PM1
1
1
0
0
SEQUENCER OPERATION
The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 10 outlines the four modes of operation of the sequencer.
Table 10. Sequence Selection
SEQ
0
0
1
1
SHADOW
0
1
0
1
PM0
1
0
1
0
Mode
Normal Operation. In this mode, the AD7908/AD7918/AD7928 remain in full power mode regardless of the status of any of
the logic inputs. This mode allows the fastest possible throughput rate from the AD7908/AD7918/AD7928.
Full Shutdown. In this mode, the AD7908/ AD7918/AD7928 is in full shutdown mode with all circuitry powering down. The
AD7908/AD7918/AD7928 retains the information in the control register while in full shutdown. The part remains in full
shutdown until these bits are changed.
Auto Shutdown. In this mode, the AD7908/AD7918/AD7928 automatically enters full shutdown mode at the end of each
conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs
has elapsed before attempting to perform a valid conversion on the part in this mode.
Invalid Selection. This configuration is not allowed.
Sequence Type
This configuration means that the sequence function is not used. The analog input channel selected for each individual
conversion is determined by the contents of the ADD0 through ADD2 channel address bits in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer
function being used, where each write to the AD7908/AD7918/AD7928 selects the next channel for conversion (see
Figure 11).
This configuration selects the SHADOW register for programming. The following write operation loads the contents of
the SHADOW register. This programs the sequence of channels to be converted on continuously with each successive
valid CS falling edge (see the
selected need not be consecutive.
If the SEQ and SHADOW bits are set in this way, then the sequence functions are not interrupted upon completion of
the write operation. This allows other bits in the control register to be altered between conversions while in a sequence,
without terminating the cycle.
This configuration is used in conjunction with the ADD2 to ADD0 channel address bits to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the
channel address bits in the control register (see Figure 13).
SHADOW Register
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section, SHADOW register bit map, and
Figure 12
). The channels