AD7490 Analog Devices, AD7490 Datasheet - Page 12

• Manufacturer Part Number: AD7490
• Description: 16-Channel, 1MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7490

• Resolution (bits): 12bit
• # Chan: 16
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7490
INTERNAL REGISTER STRUCTURE
CONTROL REGISTER
The control register on the AD7490 is a 12-bit, write-only
register. Data is loaded from the DIN pin of the AD7490 on the
falling edge of SCLK. The data is transferred on the DIN line at
the same time as the conversion result is read from the part.
The data transferred on the DIN line corresponds to the
Table 5. Control Register
MSB
11
WRITE
Table 6. Control Register Bit Functions
Bit
11
10
9 to 6
5, 4
3
2
1
0
Name
WRITE
SEQ
ADD3 to
ADD0
PM1, PM0
SHADOW
WEAK/TRI
RANGE
CODING
10
SEQ
9
ADD3
Description
The value written to this bit of the control register determines whether the following 11 bits are loaded to the
control register or not. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the
remaining 11 bits are not loaded to the control register, and it remains unchanged.
The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer
function and access the Shadow register (see Table 9).
These four address bits are loaded at the end of the present conversion sequence and select which analog input
channel is to be converted on in the next serial transfer, or they may select the final channel in a consecutive
sequence, as described in Table 9. The selected input channel is decoded as shown in Table 7. The next channel to
be converted on is selected by the mux on the 14
conversion result are also output on DOUT prior to the 12 bits of data (see the Serial Interface section).
Power management bits. These two bits decode the mode of operation of the AD7490, as shown in Table 8.
The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer
function and access the Shadow register (see Table 9).
This bit selects the state of the DOUT line at the end of the current serial transfer. If it is set to 1, the DOUT line is
weakly driven to the ADD3 channel address bit of the ensuing conversion. If this bit is set to 0, DOUT returns to
three-state at the end of the serial transfer. See the Control Register section for more details.
This bit selects the analog input range to be used on the AD7490. If it is set to 0, the analog input range extends
from 0 V to 2 × REF
For 0 V to 2 × REF
This bit selects the type of output coding used by the AD7490 for the conversion result. If this bit is set to 0, the
output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight
binary (for the next conversion).
8
ADD2
7
ADD1
IN
, V
IN
. If it is set to 1, the analog input range extends from 0 V to REF
DD
= 4.75 V to 5.25 V.
6
ADD0
Rev. C | Page 12 of 28
5
PM1
4
PM0
AD7490 configuration for the next conversion. This requires
16 serial clocks for every data transfer. Only the information
provided on the first 12 falling clock edges (after the CS falling
edge) is loaded to the control register. MSB denotes the first bit
in the data stream. The bit functions are outlined in
th
SCLK falling edge. The address bits corresponding to the
3
SHADOW
2
WEAK/TRI
IN
(for the next conversion).
1
RANGE
Table 5
LSB
0
CODING
.