AD7490 Analog Devices, AD7490 Datasheet - Page 22

• Manufacturer Part Number: AD7490
• Description: 16-Channel, 1MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7490

• Resolution (bits): 12bit
• # Chan: 16
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7490
SERIAL INTERFACE
Figure 27 shows the detailed timing diagram for serial interfacing
to the AD7490. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7490 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold goes
back into track on the 14
Figure 27
register, in which case the track-and-hold does not return to
track until the rising edge of
On the 16
three-state (assuming the WEAK/
serial clock cycles are required to perform the conversion
process and to access data from the AD7490. The 12 bits of
conversion data are preceded by the four channel address bits,
DOUT
SCLK
DOUT
SCLK
DIN
CS
DIN
CS
at point B, except when the write is to the Shadow
th
THREE-
SCLK falling edge, the DOUT line goes back into
STATE ADD3
THREE-
STATE ADD3
t
3
t
3
t
WRITE
2
t
2
th
V
1
t
IN
SCLK falling edge, as shown in
3
ADD2
0
b
1
CS , that is, Point C in
ADD2
t
SEQ
9
t
9
V
TRI bit is set to 0). Sixteen
2
IN
1
ADD1
FOUR IDENTIFICATION BITS
2
ADD1
ADD3
FOUR IDENTIFICATION BITS
V
3
IN
2
ADD0
Figure 28. Writing to Shadow Register Timing Diagram
t
3
4
ADD2
ADD0
t
Figure 28
4
Figure 27. Serial Interface Timing Diagram
V
4
IN
3
DB11
4
t
ADD1
DB11
6
.
Rev. C | Page 22 of 28
t
CONVERT
t
6
t
V
10
t
5
IN
CONVERT
4
DB10
t
10
t
5
7
ADD0
DB10
t
7
V
6
IN
ADD3 to ADD0, identifying which channel the conversion
result corresponds to. CS going low allows the ADD3 address
bit to be read in by the microprocessor or DSP. The remaining
address bits and data bits are then clocked out by subsequent
SCLK falling edges, beginning with the second address bit,
ADD2. Thus, the first SCLK falling edge on the serial clock has
the ADD3 address bit provided and also clocks out address bit
ADD2. The final bit in the data transfer is valid on the 16
falling edge, having being clocked out on the previous (15
falling edge.
Writing information to the control register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the
MSB, that is, the WRITE bit, has been set to 1. If the control
register is programmed to use the Shadow register, writing
information to the Shadow register takes place on all 16 SCLK
falling edges in the next serial transfer (see Figure 28). The
Shadow register is updated upon the rising edge of CS , and the
track-and-hold begins to track the first channel selected in the
sequence.
5
6
13
DB2
13
DONTC
DB2
B
V
14
t
IN
5
13
DB1
14
t
5
DONTC
DB1
V
15
IN
14
t
DB0
11
t
15
8
DONTC
t
DB0
11
t
8
V
16
IN
15
16
t
QUIET
THREE-
STATE
THREE-
STATE
C
th
th
)