AD7866 Analog Devices, AD7866 Datasheet - Page 18

• Manufacturer Part Number: AD7866
• Description: Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7866

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7866
POWER VS. THROUGHPUT RATE
When the AD7866 is in partial power-down mode and not
converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 21 shows that as the through-
put rate is reduced, the part remains in its partial power-down
state longer, and the average power consumption over time
drops accordingly.
For example, if the AD7866 is operated in a continuous sampling
mode with a throughput rate of 100 kSPS and an SCLK of
20 MHz (V
down mode between conversions, the power consumption is
calculated as follows. The maximum power dissipation during
normal operation is 24 mW (V
allowed from partial power-down is one dummy cycle, i.e., 1 µs,
(assuming use of an external reference) and the remaining
conversion time is another cycle, i.e., 1 µs, then the AD7866
Figure 21. Power vs. Throughput for Partial Power-Down
D
SCLK
0.01
OUT
100
0.1
10
CS
D
D
1
SCLK
A
OUT
OUT
0
CS
A
B
THREE-
STATE
DD
THREE-
STATE
50
= 5 V), and the device is placed in partial power-
SCLK = 20MHz
V
0
DD
1 LEADING ZERO
3 STATUS BITS
1
= 5V
RANGE
t
100
3
0
t
2
1
THROUGHPUT – kSPS
t
1 LEADING ZERO
3 STATUS BITS
3
RANGE
t
2
2
A0/ A0
150
DD
V
SCLK = 20MHz
2
DD
3
ZERO
200
= 5 V). If the power-up time
= 3V
A0
Figure 23. Reading Data from Both ADCs on One D
4
3
DB11
250
A/B
t
t
6
4
A
Figure 22. Serial Interface Timing Diagram
t
5
5
300
4
DB11
t
t
14
4
6
350
DB1
t
5
7
A
DB10
15
DB0
A
–18–
16
t
7
ZERO
can be said to dissipate 24 mW for 2 µs during each conversion
cycle. For the remainder of the conversion cycle, 8 µs, the part
remains in partial power-down mode. The AD7866 can be said to
dissipate 2.8 mW for the remaining 8 µs of the conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 µs and the
average power dissipated during each cycle is (2/10)
(8/10)
and the device is again in partial power-down mode between
conversions, the power dissipated during normal operation is
11.4 mW. The AD7866 can be said to dissipate 11.4 mW for 2 µs
during each conversion cycle and 1.68 mW for the remaining 8 µs
when the part is in partial power-down. With a throughput rate of
100 kSPS, the average power dissipated during each conversion
cycle is (2/10)
Figure 21 shows the maximum power versus throughput rate
when using the partial power-down mode between conversions
with both 5 V and 3 V supplies for the AD7866.
SERIAL INTERFACE
Figure 22 shows the detailed timing diagram for serial interfacing
to the AD7866. The serial clock provides the conversion clock
and controls the transfer of information from the AD7866
during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. Once 13 SCLK falling
edges have elapsed, the track-and-hold will go back into track
on the next SCLK rising edge, as shown in Figure 22 at point
B. On the rising edge of CS, the conversion will be terminated
and D
not brought high but is instead held low for a further 16 SCLK
cycles on D
1 LEADING ZERO
3 STATUS BITS
13
17
RANGE
B
DB2
OUT
(2.8 mW) = 7.04 mW. If V
A and D
OUT
A0/ A0
14
t
5
DB1
A, the data from conversion B will be output on
(11.4 mW) + (8/10)
OUT
ONE
15
OUT
B will go back into three-state. If CS is
DB11
Line
DB0
t
8
B
16
THREE-
STATE
DD
(1.68 mW) = 3.624 mW.
DB1
= 3 V, SCLK = 20 MHz,
t
B
QUIET
DB0
t
9
32
B
(24 mW) +
THREE-
STATE
REV. A