AD7676 Analog Devices, AD7676 Datasheet - Page 15

• Manufacturer Part Number: AD7676
• Manufacturer: Analog Devices

Specifications of AD7676

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

SERIAL INTERFACE
The AD7676 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7676 outputs 16 bits of data
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7676 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7676 also
generates a SYNC signal to indicate to the host when the serial
REV. B
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Conversion)
SDOUT
CS, RD
CNVST
SDOUT
CNVST
BUSY
SYNC
CS, RD
SCLK
BUSY
SYNC
SCLK
t
16
Figure 17. Master Serial Data Timing for Reading (Read after Conversion)
t
3
t
t
15
16
t
t
t
EXT/INT = 0
14
15
14
t
29
t
X
17
t
t
22
18
EXT/INT = 0
t
1
t
D15
3
t
X
20
1
t
22
t
19
t
21
t
20
D14
t
D15
23
2
1
t
t
19
18
RDC/SDIN = 1
RDC/SDIN = 0
D14
t
t
3
21
2
23
–15–
t
data is valid. The serial clock SCLK and the SYNC signal can be
inverted if desired. The output data is valid on both the rising
and falling edges of the data clock. Depending on RDC/SDIN
input, the data can be read after each conversion or during the
following conversion. Figures 17 and 18 show the detailed timing
diagrams of these two modes.
Usually, because the AD7676 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended serial mode when it can be used.
28
3
14
D2
INVSCLK = INVSYNC = 0
INVSCLK = INVSYNC = 0
14
D2
15
D1
15
D1
16
t
24
t
16
30
D0
t
24
D0
t
t
t
t
t
t
25
26
26
27
25
27
AD7676