AD7899 Analog Devices, AD7899 Datasheet - Page 4

• Manufacturer Part Number: AD7899
• Description: 5 V Single Supply 14-Bit 400 kSPS ADC
• Manufacturer: Analog Devices

Specifications of AD7899

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 400kSPS
• Interface: Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 2.5V,Bip 5.0V,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: SOIC,SOP

TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
Read Operation
External Clock
NOTES
1
2
3
4
5
Specifications subject to change without notice.
AD7899
to T
CONV
ACQ
EOC
WAKE-UP
1
2
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V
See Figures 5, 6, 7, and 8.
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V.
Refer to the Standby Mode Operation section.
t
t
t
t
t
t
t
t
t
3
4
5
6
7
8
9
10
11
MAX
3
4
and valid for V
– External V
DRIVE
REF
5
= 3 V
5% and 5 V
A, B and S
Versions
2.2
2.46
0.3
120
180
2
35
70
0
0
35
35
40
5
30
0
0
20
100
1, 2
(V
DD
5% unless otherwise noted.)
OUTPUT
= 5 V
PIN
TO
Unit
µs max
µs max
µs max
ns min
ns max
µs max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
50pF
5%, AGND = DGND = 0 V, V
1.6mA
400 A
Test Conditions/Comments
Conversion Time, Internal Clock
CLKIN = 6.5 MHz
Acquisition Time
EOC Pulsewidth
STBY Rising Edge to CONVST Rising Edge
(See Standby Mode Operation)
CONVST Pulsewidth
CONVST Rising Edge to BUSY Rising Edge
CS to RD Setup Time
CS to RD Hold Time
Read Pulsewidth
Data Access Time after Falling Edge of RD, V
Data Access Time after Falling Edge of RD, V
Bus Relinquish Time after Rising Edge of RD
BUSY Falling Edge to RD Delay
CLKIN to CONVST Rising Edge Setup Time
CLKIN to CONVST Rising Edge Hold Time
CONVST Rising Edge to CLK Falling Edge
1.6V
REF
= Internal, Clock = Internal; All specifications T
DRIVE
) and timed from a voltage level of V
DRIVE
DRIVE
DRIVE
= 5 V
= 3 V
/2.
MIN