AD7707 Analog Devices, AD7707 Datasheet
AD7707
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AD7707 Summary of contents
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... V. Its bipolar input signal ranges are ±10 mV through ±1.225 V. The high level input channel can accept input signal ranges of ±10 V, ± and The AD7707 thus performs all signal conditioning and conversion for a 3-channel system. ...
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... Digital Interface .............................................................................. 36 Configuring the AD7707 ............................................................... 37 Microcomputer/Microprocessor Interfacing .............................. 39 AD7707 to 68HC11 Interface .................................................. 39 AD7707 to 8XC51 Interface ..................................................... 40 Code For Setting Up the AD7707 ................................................ 41 C Code for Interfacing AD7707 to 68HC11 ........................... 41 Applications Information .............................................................. 43 Data Acquisition ......................................................................... 43 Smart Valve/Actuator Control .................................................. 43 Pressure Measurement ............................................................... 45 ...
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... Changes to Table 16 ........................................................................ 19 Changes to Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0); Power-On/Reset Status: 0x1F4000 Section .................... 22 Changes to Calibration Sequences Section .................................. 23 Changes to Circuit Description Section ....................................... 24 Deleted Evaluating the AD7707 Performance Section .............. 27 Changes to Digital Filtering Section and Filter Characteristics Section ......................................................... 28 Deleted AD7707 to ADSP-2103/ADSP-2105 Interface Section .............................................................................................. 31 Deleted Figure 23 ...
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... AD7707 SPECIFICATIONS REF IN(+) = 1.225 V with MCLK IN = 2.4576 MHz unless otherwise noted. All specifications T Table 1. Parameter STATIC PERFORMANCE Low Level Input Channels (AIN1 and AIN2) No Missing Codes Output Noise 2 Integral Nonlinearity Unipolar Offset Error 3 4 Unipolar Offset Drift ...
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... V min/V max 0.4/0.8 V min/V max 1/2.5 V min/V max 0.4/1.1 V min/V max 0.375/0.8 V min /V max Rev Page AD7707 Conditions/Comments For filter notches of 10 Hz, 20 Hz, 60 Hz, ±0.02 × f BUF bit of setup register = 0 BUF bit of setup register = 1 BUF = 0 Unipolar input range ( B /U bit of setup register = 1) B Bipolar input range ( ...
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... AD7707 Parameter MCLK IN Only V , Input Low Voltage INL V , Input High Voltage INH MCLK IN Only V , Input Low Voltage INL V , Input High Voltage INH LOGIC OUTPUTS (Including MCLK OUT Output Low Voltage Output High Voltage OH Floating State Leakage Current 14 Floating State Output Capacitance ...
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... Rev Page AD7707 Conditions/Comments digital inputs = MCLK IN excluding dissipation in the AIN3 attenuator Typically 0.84 mW; BUF = MHz, all gains CLK IN Typically 1.53 mW; BUF = MHz; all gains CLK IN Typically 1.11 mW; BUF = ...
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... See Figure 20 and Figure 21 duty cycle range is 45% to 55%. f must be supplied whenever the AD7707 is not in standby mode clock is present in this case, the device can draw CLKIN CLKIN higher current than specified and possibly become uncalibrated. 4 The AD7707 is production tested with ...
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... V to +30 V −0 0 −0 0 −0 0 −0 0 −0 0 −40°C to +85°C −65°C to +150°C 150°C 450 mW 75°C/W 260°C 450 mW 139°C/W 260°C 2.5 kV Rev Page AD7707 ...
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... CS Chip Select. This pin is an active low logic input used to select the AD7707. With this input hard-wired low, the AD7707 can operate in its 3-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus frame synchronization signal in communicating with the AD7707 ...
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... Serial Data Input with Serial Data Being Written to the Input Shift Register on the Part. Data from this input shift register is transferred to the setup register, clock register, or communications register, depending on the register selection bits of the communications register Digital Supply Voltage, 2 5.25 V Operation DGND Ground Reference Point for the AD7707’s Internal Digital Circuitry. Rev Page AD7707 ...
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... AD7707 TYPICAL PERFORMANCE CHARACTERISTICS 32,771 25° 2.5V RMS NOISE = 600nV REF 32,770 GAIN = 128 50Hz UPDATE RATE 32,769 32,768 32,767 32,766 32,765 32,764 32,763 0 100 200 300 400 500 600 READING NUMBER Figure 4. Typical Noise Plot at Gain = 128 with 50 Hz Update Rate for Low ...
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... OSCILLATOR = 4.9152MHz 2 OSCILLATOR = 2.4576MHz CH1 5.00V CH2 2.00V Figure 10. Typical Crystal Oscillator Power-Up Time 5ms/DIV –40 –30 –20 –10 Figure 11. Standby Current vs. Temperature Rev Page AD7707 MCLK ...
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... OUTPUT NOISE OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (5 V OPERATION) Table 7 shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the bipolar input ranges with ...
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... OUTPUT NOISE FOR LOW LEVEL INPUT CHANNELS (3 V OPERATION) Table 9 shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the bipolar input ranges with ...
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... AD7707 OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (5 V OPERATION) Table 11 shows the AD7707 output rms noise and peak-to-peak resolution in unbuffered mode for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the ±10 V, ± ...
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... OUTPUT NOISE FOR HIGH LEVEL INPUT CHANNEL AIN3 (3 V OPERATION) Table 13 shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers given are for the ± and ranges with ...
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... Standby. Writing this bit puts the part into its standby or power-down mode. In this mode, the part consumes only 8 μA of power supply current. The part retains its calibration coefficients and control word information when in standby. Writing this bit places the part in its normal operating mode. The serial interface on the AD7707 remains operational when the part is in standby mode. ...
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... Table 17. Channel Selection for AD7707 CH1 CH0 AIN 0 0 AIN1 0 1 AIN2 1 0 LOCOM 1 1 AIN3 Register Communications register Setup register Clock register Data register Test register No operation Zero-scale calibration register ...
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... AD7707 Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset Status: 0x01 The setup register is an eight-bit register from which data can either be read or to which data can be written. Table 18 outlines the bit designations for the setup register. Table 18. Setup Register MD1 (0) ...
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... Bit Description Zero Zero. A zero must be written to these bits to ensure correct operation of the AD7707. Failure may result in unspecified operation of the device. CLKDIS Master clock disable bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin. When disabled, the MCLK OUT pin is forced low ...
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... Data Register (RS2, RS1, RS0 = The data register on the part is a 16-bit read-only register that contains the most up-to-date conversion result from the AD7707. If the communications register sets up the part for a write operation to this register, a write operation must actually take place to return the part to where it is expecting a write operation to the communications register ...
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... CALIBRATION SEQUENCES The AD7707 contains a number of calibration options as previously outlined. Table 25 summarizes the calibration types, the operations involved, and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor when DRDY returns low at the end of the sequence ...
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... AD7707 CIRCUIT DESCRIPTION The AD7707 is a Σ-Δ ADC with on-chip digital filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or process control applications. It contains a Σ-Δ (or charge balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter, and a bidirectional serial communica- tions port. The part consumes only 320 μ ...
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... It should be noted that the bipolar input signals are referenced to the LOCOM input. The AD7707 also has a high level analog input channel AIN3, which is referenced to HICOM. Figure 13 shows the input structure on the high level input channel. ...
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... BIPOLAR/UNIPOLAR INPUTS The analog inputs on the low level input channels on the AD7707 can accept either unipolar or bipolar input voltage ranges with respect to LOCOM. The high level input channel handles true bipolar signals of ±10 V max Bipolar or unipolar options are chosen by programming the B /U bit of the setup register ...
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... The nominal reference voltage, V REF IN(+) − REF IN(−), REF for specified operation is +2.5 V for the AD7707 operated with and 1.225 V for the AD7707 operated with The part is functional with but with degraded performance because the LSB size is smaller. REF IN(+) must always be greater than REF IN(− ...
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... FILTER CHARACTERISTICS The AD7707’s digital filter is a low-pass filter with a (sinx/x) 3 response (also called sinc ). The transfer function for this filter is described in the z domain by: 3 − ...
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... For example, if the required bandwidth is 7.86 Hz, but the required update rate is 100 Hz, the data can be taken from the AD7707 at the 100 Hz rate, giving a −3 dB bandwidth of 26.2 Hz. Postfiltering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz ...
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... AIN1 = LOCOM = internal bias voltage in the case of the AD7707. The PGA is set for the selected gain (as per the G2, G1, and G0 bits in the setup register) for this zero-scale calibration conversion. The full- ...
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... V /gain. However, the span (which is the difference between REF the bottom of the AD7707’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset that can be accommo- dated depends on whether the unipolar or bipolar mode is being used ...
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... A calibration should be performed if the update rate or gain are changed. The power dissipation and temperature drift of the AD7707 are low and no warm-up time is required before the initial calibration is performed. However external reference is being used, this reference must stabilize before calibration is initiated ...
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... The maximum recommended load on this pin is one CMOS load. When using a crystal or ceramic resonator to generate the AD7707’s clock, it may be desirable to use this clock as the clock source for the system. In this case recommended that the MCLK OUT signal is buffered with a CMOS buffer before being applied to the rest of the circuit ...
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... The RESET input on the AD7707 resets all the logic, the digital filter, and the analog modulator, while all on-chip registers are reset to their default state. DRDY is driven high and the AD7707 ignores all communications to any of its registers while the RESET input is low. When the RESET input returns high, the AD7707 starts to process data and DRDY returns low in 3 × ...
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... However, because the resolution of the AD7707 is so high, and the noise levels from the AD7707 so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7707 should be designed so that the analog and digital sections are separated and confined to certain areas of the board ...
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... The serial interface can be reset by exercising the RESET input on the part. It can also be reset by writing a series the DIN input Logic 1 is written to the AD7707 DIN line for at least 32 serial clock cycles, the serial interface is reset. This ensures that in 3-wire systems, if the interface is lost either via a software error glitch in the system, it can be reset back to a known state ...
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... CONFIGURING THE AD7707 The AD7707 contains six on-chip registers that the user can accesses via the serial interface. Communication with any of these registers is initiated by writing to the communications register first. Figure 22 outlines a flow diagram of the sequence used to configure all registers after a power-up or reset on the AD7707. The flowchart also shows two different read options— ...
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... YES READ FROM COMMUNICATIONS REGISTER POLL DRDY BIT OF COMMUNICATIONS REGISTER WRITE TO COMMUNICATIONS REGISTER SETTING UP NEXT OPERATION READ FROM THE DATA REGISTER (38 HEX) Figure 22. Flowchart for Setting Up and Reading from the AD7707 Rev Page DRDY LOW? YES READ FROM DATA REGISTER ...
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... DRDY output is connected to the IRQ input of the 68HC11. For interfaces that require control of the CS input on the AD7707, one of the port bits of the 68HC11 (such as PC1), which is configured as an output, can be used to drive the CS input. ...
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... DRDY output is connected to the INT1 input of the 8XC51. For interfaces that require control of the CS input on the AD7707, one of the port bits of the 8XC51 (such as P1.1), which is configured as an output, can be used to drive the CS input. The 8XC51 is configured in its Mode 0 serial interface mode ...
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... This C CODE FOR INTERFACING AD7707 TO 68HC11 /* This program has read and write routines for the 68HC11 to interface to the AD7707 and the sample program sets the various registers and then reads 1000 samples from one channel. */ #include < ...
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... AD7707 Writetoreg (int byteword); { int q; SPCR = 0x3f; SPCR = 0X7f; /* this sets the WiredOR mode (DWOM=1), Master mode (MSTR=1), SCK idles high (CPOL=1), /SS can be low always (CPHA=1), lowest clock speed (slowest speed which is master clock /32) */ DDRD = 0x18; /* SCK, MOSI outputs */ q = SPSR SPDR; /* the read of the status register and of the data register is needed to clear the ...
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... In addition, the 3-wire digital interface on the AD7707 allows data acquisition front ends to be isolated with just three wires. The AD7707 can be operated from a single and its low power operation ensures that very little power needs to be brought across the isolation barrier in an isolated application. ...
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... VALVE AD7707 ±10V AIN3 REF IN(+) +2.5V VBIAS HICOM REF IN(–) AGND DGND AIN1 RSENSE LOCOM Figure 26. Smart Valve/Actuator Control Using the AD7707 MAIN TRANSMITTER ASSEMBLY V 100kΩ CC 4.7µF MICROCONTROLLER UNIT •PID •RANGE SETTING •CALIBRATION •LINEARIZATION •OUTPUT CONTROL •SERIAL COMMUNICATION •HART PROTOCOL COM Figure 27 ...
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... If the buffer is required, the common-mode voltage should be MCLK OUT set accordingly by inserting a small resistance between the bottom end of the RTD and GND of the AD7707. In the application shown, an external 400 μA current source provides the excitation DRDY current for the PT100 and generates the reference voltage ...
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... AIN3 Range VBIAS ±10 V 2.5 V ± AGND 2.5 V − +10 V 2.5 V Table 29. Configuration of AD7707 vs. Input Range on AIN3 (AV AIN3 Range VBIAS ± 1.25 V − +10 V 1.25 V −7 +10 V 1.25 V ±10 V 1.666 V Table 30. Typical Input Current vs. Voltage on AIN3 ...
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... PGA. Table 31 and Table 32 show what the high level channel performance actually is over the complete range of gain settings. Table 31 shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register ...
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... AD7707 3 V OPERATION Table 33 shows the AD7707 output rms noise and peak-to-peak resolution for the selectable notch and −3 dB frequencies for the part, as selected by FS0, FS1, and FS2 of the clock register. The numbers are given for all input ranges with ...
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... Dimensions shown in millimeters and (inches) 6.60 6.50 6. 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.30 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 33. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev Page 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.75 8° 0.60 0° 0.45 AD7707 ...
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... Supply DD AD7707BR 2 5.25 V AD7707BR-REEL 2 5.25 V AD7707BRZ 2 5.25 V AD7707BRZ-REEL 2 5.25 V AD7707BRZ-REEL7 2 5.25 V AD7707BRU 2 5.25 V AD7707BRU-REEL7 2 5.25 V AD7707BRUZ 2 5.25 V AD7707BRUZ-REEL 2 5.25 V AD7707BRUZ-REEL7 2 5. RoHS Compliant Part. Temperature Range Package Description −40°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W] −40°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W] − ...
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... NOTES Rev Page AD7707 ...
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... AD7707 NOTES ©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08691-0-1/10(B) Rev Page ...