AD7707 Analog Devices, AD7707 Datasheet - Page 7

• Manufacturer Part Number: AD7707
• Manufacturer: Analog Devices

Specifications of AD7707

• Resolution (bits): 16bit
• # Chan: 3
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip
• Ain Range: Bip (Vref)/(PGA Gain),Bip 10V,Bip 5.0V,Uni (Vref)/(PGA Gain),Uni 10V,Uni 5.0V
• Adc Architecture: Sigma-Delta
• Pkg Type: SOIC,SOP

Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table 2. Low Level Input Channels, AIN1 and AIN2
Gain
AV
AV
Table 3. High Level Input Channel, AIN3
Gain
AV
AV
Temperature range as follows: B Version, −40°C to +85°C.
These numbers are established from characterization or design at initial product release.
A calibration is effectively a conversion so these errors are of the order of the conversion noise shown in Table 7 and Table 9 for the low level input channels AIN1 and
AIN2. This applies after calibration at the temperature of interest.
Recalibration at any temperature removes these drift errors.
Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
Gain error does not include zero-scale errors. It is calculated as full-scale error—unipolar offset error for unipolar ranges and full-scale error—bipolar zero error for
bipolar ranges.
Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if
Error is removed following a system calibration.
than AGND − 100 mV. Parts are functional with voltages down to AGND − 200 mV, but with increased leakage at high temperature.
respect to the HCOM input on the high level input channel, AIN3. The absolute voltage on the low level analog inputs should not go more positive than AV
100 mV, or go more negative than GND − 100 mV for specified performance. Input voltages of AGND − 200 mV can be accommodated, but with increased leakage at
high temperature.
crystal or resonator type (see the Clocking and Oscillator Circuit section).
notches of 20 Hz or 60 Hz.
ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends
on the crystal or resonator type (see the Standby Mode section).
This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AV
The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with
V
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
Sample tested at +25°C to ensure compliance.
After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.
These calibration and span limits apply provided that the absolute voltage on the analog inputs does not exceed AV
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter
PSRR depends on both gain and AV
If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA typical at 3 V. When using a crystal or
Normal Mode Power Dissipation
Normal Mode Power Dissipation
Standby (Power-Down) Current
REF
DD
DD
DD
DD
mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
= REF IN(+) − REF IN(−).
= 3 V
= 5 V
= 3 V
= 5 V
DD
20
17
17
. See Table 2 and Table 3.
1
86
90
1
68
72
B Version
1.05
2.04
1.35
2.34
2.1
3.75
3.1
4.75
18
8
1
Rev. B | Page 7 of 52
2
78
78
2
60
60
mW max
mW max
Unit
mW max
mW max
mW max
mW max
mW max
mW max
μA max
μA max
4
85
84
4
67
66
Conditions/Comments
AV
MCLK IN excluding dissipation in the AIN3 attenuator
Typically 0.84 mW; BUF = 0; f
Typically 1.53 mW; BUF = 1; f
Typically 1.11 mW; BUF = 0; f
gain = 1 to 4
Typically 1.9 mW; BUF = 1; f
gain = 1 to 4
AV
external MCLKIN
Typically 1.75 mW; BUF = 0; f
Typically 2.9 mW; BUF = 1; f
Typically 2.6 mW; BUF = 0; f
Typically 3.75 mW; BUF = 1; f
External MCLK IN = 0 V or DV
AV
External MCLK IN = 0 V or DV
AV
DD
DD
DD
DD
DD
current and power dissipation varies depending on the
= DV
= DV
= 5 V
= 3 V
zero-scale calibrations were performed.
DD
DD
DD
= 3 V; digital inputs = 0 V or DV
= 5 V; digital inputs = 0 V or DV
+ 30 mV or go more negative than AGND −
8 to 128
93
91
8 to 128
75
73
DD
+ 30 mV or go more negative
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
DD
DD
= 1 MHz; all gains
; typically 9 μA;
; typically 4 μA;
= 1 MHz, all gains
= 1 MHz; all gains
= 2.457 6 MHz;
= 2.4576 MHz
= 1 MHz; all gains
= 2.4576 MHz,
= 2.4576 MHz
AD7707
DD
DD
DD
; external
;
+