AD7854 Analog Devices, AD7854 Datasheet
AD7854
Specifications of AD7854
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AD7854 Summary of contents
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... The AD7854 is capable of 200 kHz throughput rate while the AD7854L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudo- differential sampling scheme ...
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... AD7854/AD7854L–SPECIFICATIONS External Reference MHz (for L Version: 1.8 MHz ( +70 C) and 1 MHz (– +85 C)); f CLKIN (AD7854L unless otherwise noted.) Specifications in () apply to the AD7854L. A MIN MAX Parameter A Version DYNAMIC PERFORMANCE 3 Signal to Noise + Distortion Ratio 70 (SNR) Total Harmonic Distortion (THD) – ...
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... The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V and the allowable system full-scale voltage applied between AIN(+) and AIN(– ...
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... The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8 MHz master clock. Specifications subject to change without notice MHz for AD7854 and 1.8 MHz for AD7854L CLKIN ...
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... DB0 DB1 14 15 Model AD7854AQ AD7854SQ AD7854AR AD7854BR AD7854ARS 3 AD7854LAQ 3 AD7854LAR 3 AD7854LARS 4 EVAL-AD7854CB EVAL-CONTROL BOARD NOTES 1 Linearity error refers to the integral linearity error Cerdip SOIC SSOP signifies the low power version. 4 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes ...
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... HBEN High Byte Enable Input. The AD7854 operates in byte mode only but outputs 12 bits of data during a read cycle with HBEN low. When HBEN is high, then the high byte of data that is written to or read from the part is on DB0 to DB7. When HBEN is low, then the lowest byte of data being written to the part is on DB0 to DB7 ...
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... Signal to (Noise + Distortion) = (6. 1.76) dB Thus for a 12-bit converter, this is 74 dB. REV. B Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7854/AD7854L defined as: THD (dB log where V is the rms amplitude of the fundamental and V ...
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... AD7854/AD7854L AD7854/AD7854L ON-CHIP REGISTERS The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7854/AD7854L will operate as a read-only ADC. The WR pin should be tied to DV read-only ADC. Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali- bration, and software conversion start can be selected by writing to the part ...
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... First the system gain error is calibrated out followed by the system offset error. The system offset error only is removed. The system gain error only is removed. –9– AD7854/AD7854L PMGT0 RDSLT1 CALSLT0 STCAL LSB ) ...
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... AD7854/AD7854L STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register are described below. The power-up status of all bits is 0. ...
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... CALIBRATION REGISTERS The AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. ...
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... AD7854/AD7854L START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST REGISTER READ OPERATION OR ABORT ? YES FINISHED Figure 7. Flowchart for Reading from the Calibration ...
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... CONVST rising edge. Reading/writing during conversion typically de- grades the Signal to (Noise + Distortion) by less than 0.5 dBs. The AD7854 can operate at throughput rates of over 200 kSPS (up to 100 kSPS for the AD7854L). With the AD7854L, 100 kSPS throughput can be obtained as follows: the CLKIN and CONVST signals are arranged to give a conversion time of 16 ...
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... DAC In a single supply application (both 3 V and 5 V), the V+ and V– of the op amp can be taken directly from the supplies to the AD7854/AD7854L which eliminates the need for extra external power supplies. When operating with rail-to-rail inputs and out- COMPARATOR HOLD puts at frequencies greater than 10 kHz, care must be taken in selecting the particular op amp for the application ...
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... Input Ranges The analog input range for the AD7854/AD7854L both the unipolar and bipolar ranges. REF The only difference between the unipolar range and the bipolar range is that in the bipolar range the AIN(–) should be biased least +V ...
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... F C REF1 0 REF2 0.01 F REF /REF IN 0.01 F Figure 17. Relevant Connections, AV AD7854/AD7854L PERFORMANCE CURVES Figure 18 shows a typical FFT plot for the AD7854 at 200 kHz sample rate and 10 kHz input frequency. 0 /REF pin. These –20 IN OUT –40 pin and a 100 nF OUT –60 –80 – ...
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... The AD7854/AD7854L powers up from a full software power- down in 5 µs typ. This limits the throughput which the part is capable of to 100 kSPS for the AD7854 and 60 kSPS for the AD7854L when powering down between conversions. Figure 21 shows how a full power-down between conversions is implemented using the CONVST pin ...
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... IN has a conversion time of 4.6 µs with a 4 MHz external clock, and the AD7854L has a conversion time of 9 µs with a 1.8 MHz clock. This means the AD7854/AD7854L consumes 4.5 mA/ 1.5 mA typ for 9.6 µs/14 µs in every conversion cycle if the parts are powered down at the end of a conversion. The four graphs, ...
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... THROUGHPUT RATE – kSPS Figure 24. Power vs. Throughput AD7854 AD7854L FULL POWER-DOWN CLKIN = 1.8MHz DD 1 ON-CHIP REFERENCE 0.1 0. THROUGHPUT RATE – kSPS Figure 25. Power vs. Throughput AD7854L REV AD7854 FULL POWER-DOWN V DD ON-CHIP REFERENCE 1 0.1 0. Figure 26. Power vs. Throughput AD7854 10 ...
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... STCAL bit to 1. The duration of each of the different types of calibration is given in Table IX for the AD7854 with a 4 MHz master clock. These calibration times are master clock dependent. Therefore the calibration times for the AD7854L (CLKIN = 1.8 MHz) are larger than those quoted in Table VIII ...
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... Figure 29. System Calibration Description System calibration allows the user to remove system errors external to the AD7854/AD7854L, as well as remove the errors of the AD7854/AD7854L itself. The maximum calibration range for the system offset errors is ± system gain errors it is ± 2. ...
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... AD7854/AD7854L System Gain and Offset Interaction The architecture of the AD7854/AD7854L leads to an interac- tion between the system offset and gain errors when a system calibration is performed. Therefore it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. When a system offset calibration is performed, the system offset error is reduced to zero ...
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... DATA VALID Figure 35. Read Cycle Timing Diagram Using CS and RD In the case where the AD7854/AD7854L is operated as a read- only ADC, the WR pin can be tied permanently high. The read operation need only consist of one read if the system has a 12- bit or a 16-bit data bus. ...
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... A parallel interface between the AD7854/AD7854L and the TMS32020, TMS320C25 and TMS320C5x family of DSPs are shown in Figure 39. The memory mapped addresses chosen for the AD7854/AD7854L should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7854/AD7854L is fast enough to interface to the TMS32020 with no extra wait states. In the ...
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... Figure 41 shows a parallel interface between the AD7854/ AD7854L and the DSP5600x series of DSPs. The AD7854/ AD7854L should be mapped into the top 64 locations of Y data memory. If extra wait states are needed in this interface, they can be programmed using the Port A bus control register (please see DSP5600x User’ ...
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... The analog ground plane should be allowed to run under the AD7854/AD7854L to avoid noise coupling. The power supply lines to the AD7854/AD7854L should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast ...
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... System Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . 22 PARALLEL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Resetting the Parallel Interface . . . . . . . . . . . . . . . . . . . . . 23 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 24 AD7854/AD7854L to ADSP-21xx . . . . . . . . . . . . . . . . . . 24 AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AD7854/AD7854L to TMS320C30 . . . . . . . . . . . . . . . . 25 AD7854/AD7854L to DSP5600x . . . . . . . . . . . . . . . . . . 25 APPLICATIONS HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Evaluating the AD7854/AD7854L Performance . . . . . . . 26 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE INDEX # Title I Write Register Addressing . . . . . . . . . . . . . . . . . . . . . . . 8 II Read Register Addressing ...
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... AD7854/AD7854L 0.005 (0.13) MIN 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Cerdip (Q-28) 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70 PIN 1 0.015 1.490 (37.85) MAX (0.38) MIN 0.150 (3.81) MIN 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) SEATING PLANE ...