AD7854 Analog Devices, AD7854 Datasheet - Page 24

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

AD7854/AD7854L
MICROPROCESSOR INTERFACING
The parallel port on the AD7854/AD7854L allows the device to
be interfaced to microprocessors or DSP processors as a memory
mapped or I/O mapped device. The CS and RD inputs are
common to all memory peripheral interfacing. Typical inter-
faces to different processors are shown in Figures 38 to 41.
In all the interfaces shown, an external timer controls the
CONVST input of the AD7854/AD7854L and the BUSY out-
put interrupts the host DSP. Also, the HBEN pin is connected
to address line A0 (XA0 in the case of the TMS320C30). This
maps the AD7854/AD7854L to two locations in the processor
memory space, ADCaddr and ADCaddr+1. Thus when writing
to the ADC, first the 8 LSBs of the 16-bit are written to address
location ADCaddr and then the 8 MSBs to location ADCaddr+1.
All the interfaces use a 12-bit data bus, so only one read is needed
from location ADCaddr to access the ADC output data register
or the status register. To read from the other registers, the
8 MSBs must be read from location ADCaddr+1. Interfacing
to 8-bit bus systems is similar, except that two reads are
required to obtain data from all the registers.
AD7854/AD7854L to ADSP-21xx
Figure 38 shows the AD7854/AD7854L interfaced to the
ADSP-21xx series of DSPs as a memory mapped device. A
single wait state may be necessary to interface the AD7854/
AD7854L to the ADSP-21xx depending on the clock speed of
the DSP. This wait state can be programmed via the data
memory waitstate control register of the ADSP-21xx (please see
ADSP-2100 Family Users Manual for details). The following
instruction reads data from the AD7854/AD7854L:
Data can be written to the AD7854/AD7854L using the
instructions:
where ADCaddr is the address of the AD7854/AD7854L in
ADSP-21xx data memory, AX0 contains the data read from the
ADC, and AY 0 contains the 8 LSBs and AY 1 the 8 MSBs of
data written to the AD7854/AD7854L.
Figure 38. AD7854/AD7854L to ADSP-21xx Parallel Interface
AX 0 = DM(ADCaddr)
DM (ADCaddr) = AY 0
DM (ADCaddr+1) = AY 1
*ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-21xx*
A13–A1
D23–D8
IRQ2
DMS
WR
RD
A0
ADDRESS BUS
EN
DATA BUS
DECODE
ADDR
CS
HBEN
WR
RD
BUSY
DB11–DB0
AD7854/
AD7854L*
–24–
AD7854/AD7854L to TMS32020, TMS320C25 and TMS320C5x
A parallel interface between the AD7854/AD7854L and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 39. The memory mapped addresses chosen for
the AD7854/AD7854L should be chosen to fall in the I/O
memory space of the DSPs.
The parallel interface on the AD7854/AD7854L is fast enough
to interface to the TMS32020 with no extra wait states. In the
TMS320C25 interface, data accesses may be slowed sufficiently
when reading from and writing to the part to require the inser-
tion of one wait state. In such a case, this wait state can be
generated using the single OR gate to combine the CS and
MSC signals to drive the READY line of the TMS320C25, as
shown in Figure 39. Extra wait states are necessary when using
the TMS320C5x at their fastest clock speeds. Wait states can
be programmed via the IOWSR and CWSR registers (please see
TMS320C5x User Guide for details).
Data is read from the ADC using the following instruction:
where D is the memory location where the data is to be stored
and ADCaddr is the I/O address of the AD7854/AD7854L.
Data is written to the ADC using the following two instructions:
where D8LSB is the memory location where the 8 LSBs of data
are stored, D8MSB is the location where the 8 MSBs of data are
stored and ADCaddr and ADCaddr+1 are the I/O memory
spaces that the AD7854/AD7854L is mapped into.
Figure 39. AD7854/AD7854L to TMS32020/C25/C5x
Parallel Interface
IN D,ADCaddr
OUT D8LSB, ADCaddr
OUT D8MSB, ADCaddr+1
*ADDITIONAL PINS OMITTED FOR CLARITY
TMS32020/
TMS320C25/
TMS320C50*
A15–A1
D23–D0
READY
STRB
MSC
INTx
R/W
A0
IS
ADDRESS BUS
EN
DATA BUS
DECODE
ADDR
TMS320C25
ONLY
CS
HBEN
WR
RD
BUSY
DB11–DB0
AD7854/
AD7854L*
REV. B