AD7858 Analog Devices, AD7858 Datasheet
AD7858
Specifications of AD7858
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AD7858 Summary of contents
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... The part powers up with a set of default conditions and can operate as a read-only ADC. The AD7858 is capable of 200 kHz throughput rate while the AD7858L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudo-differential sampling scheme ...
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... Floating-State Leakage Current 4 Floating-State Output Capacitance 10 Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 4.6 (18) Track/Hold Acquisition Time 0 unless otherwise noted.) Specifications apply to the AD7858L. A MIN MAX Version Units Test Conditions/Comments 71 dB min Typically SNR –78 ...
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... The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± ...
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... The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8/1 MHz master clock. Specifications subject to change without notice MHz for AD7858 and 1.8/1 MHz for AD7858L CLKIN ...
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... Figures 2 and 3 show typical read and write timing diagrams for serial Interface Mode 2. The reading and writing occurs after conversion in Figure 2, and during conversion in Figure 3. To attain the maximum sample rate of 100 kHz (AD7858L) or 200 kHz (AD7858), reading and writing must be performed during conversion as in Figure 3. At least 400 ns acquisition ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7858/AD7858L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as an input pin I/O pin depending on the serial interface mode the part is in (see Table X). 22 CLKIN Master clock signal for the device (4 MHz AD7858, 1.8 MHz AD7858L). Sets the conversion and cali- bration times. 23 SCLK Serial Port Clock ...
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... AIN(+) refers to the positive input of the pseudo differential pair, and AIN(–) refers to the negative analog input of the pseudo differential pair or to AGND depending on the channel configuration. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7858/AD7858L defined as ...
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... Addressing the On-Chip Registers Writing A write operation to the AD7858/AD7858L consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which register is addressed, and the subsequent 14 bits of data are written to the addressed register not until all 16 bits are written that the data is latched into the addressed registers. Table I shows the decoding of the address bits while Figure 4 shows the overall write register hierarchy ...
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... AD7858/AD7858L CONTROL REGISTER The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de- scribed below. The power-up status of all bits is 0. ...
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... AD7858/AD7858L sample and hold circuit, *AIN(–) refers to the negative input seen by the AD7858/AD7858L sample and hold circuit. CALMD CALSLT1 CALSLT0 ...
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... AD7858/AD7858L STATUS REGISTER The arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register are described below. The power-up status of all bits is 0. ...
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... CALIBRATION REGISTERS The AD7858/AD7858L has 10 calibration registers in all, eight for the DAC, one for the offset, and one for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers ...
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... AD7858/AD7858L START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST REGISTER READ OPERATION OR ABORT ? YES FINISHED Adjusting the Offset Calibration Register The offset calibration register contains 16 bits, two leading zeros, and 14 data bits ...
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... CONVST rising edge. However, the maximum throughput rates are achieved by reading/writing during conver- sion, and reading/writing during conversion is likely to degrade the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858 can operate at throughput rates up to 200 kHz, 100 kHz for the AD7858L. For the AD7858 a conversion takes 18 CLKIN periods ...
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... In a single supply application (both 3 V and 5 V), the V+ and V– of the op amp can be taken directly from the supplies to the AD7858/AD7858L which eliminates the need for extra external power supplies. When operating with rail-to-rail inputs and outputs, at frequencies greater than 10 kHz care must be taken ...
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... Input Range The analog input range for the AD7858/AD7858L The AIN(–) pin on the AD7858/AD7858L can be biased REF up above AGND, if required. The advantage of biasing the lower end of the analog input range away from AGND is that the user does not need to have the analog input swing all the way down to AGND ...
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... AD7858/AD7858L PERFORMANCE CURVES Figure 18 shows a typical FFT plot for the AD7858 at 200 kHz sample rate and 10 kHz input frequency SAMPLE – SNR = 72.04dB THD = –88.43dB –40 –60 –80 –100 –120 FREQUENCY – kHz Figure 19 shows the SNR vs. Frequency for different supplies and different external references ...
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... The AD7858 powers up from a full hardware or software power-down in 5 µs typ. This limits the throughput which the part is capable of to 104 kSPS for the AD7858 operating with a 4 MHz CLK and 66 kSPS for the AD7858L with a 1.8 MHz CLK when powering down between conversions. Figure 22 shows how power-down between conversions is implemented using the CONVST pin ...
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... When using this mode of operation, the AD7858 is only powered up for the duration of the conver- sion. If the power-up time of the AD7858 is taken µs and it is assumed that the current during power- typ, then power consumption as a function of throughput can easily be calculated. The AD7858 has a conversion time of 4.6 µ ...
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... BUSY (O/P) t System Calibration Description System calibration allows the user to take out system errors external to the AD7858/AD7858L as well as calibrate the errors of the AD7858/AD7858L itself. The maximum calibration range for the system offset errors is ± system gain errors is ± 2. This means that the maxi- ...
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... REF System Gain and Offset Interaction The inherent architecture of the AD7858/AD7858L leads to an interaction between the system offset and gain errors when a system calibration is performed. Therefore recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. Separate system offset and system gain calibrations reduce the offset and gain errors to at least the 12-bit level ...
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... SERIAL INTERFACE SUMMARY Table IX details the two interface modes and the serial clock edges from which the data is clocked out by the AD7858/ AD7858L (DOUT Edge) and that the data is latched in on (DIN Edge). In both interface Modes 1 and 2 the SYNC is gated with the SCLK. Thus the SYNC↓ ...
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... AD7858/AD7858L DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) The read and writing takes place on the DIN line and the con- version is initiated by pulsing the CONVST pin (note that in every write cycle the 2/3 MODE bit must be set to 1). The conversion may be started by setting the CONVST bit in the control register to 1 instead of using the CONVST pin ...
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... SCLK) (5V/3V DB15 DB14 DB13 DB12 DB11 DB14 DB13 DB12 DB11 DB10 SYNC AD7858/AD7858L after the SYNC goes high MIN/MAX (CONTINUOUS SCLK), = 20/30ns MIN (5V/3V MIN/MAX SCLK THREE-STATE DB10 DB0 DB0 be- 7 ...
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... To enable Serial Interface Mode 1 the user must also write to the part. Figure 34 and 35 outline flowcharts of how to configure the AD7858/ AD7858L Serial Interface Modes 1 and 2 respectively. The continuous loops on all diagrams indicate the sequence for more ...
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... WAIT FOR BUSY SIGNAL TO GO LOW OR WAIT FOR BUSY BIT = 0 WAIT FOR BUSY SIGNAL TO GO LOW APPLY SYNC (IF REQUIRED), SCLK, READ CURRENT CONVERSION RESULT ON DOUT PIN, AND WRITE CHANNEL SELECTION AD7858/AD7858L TRANSFER YES DATA DURING CONVERSION ? APPLY SYNC (IF REQUIRED), SCLK, WRITE TO CONTROL REGISTER SETTING CHANNEL, ...
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... Figure 38 shows the AD7858/AD7858L SPI/QSPI interface to the 68HC11/16/L11/PIC16C42. The 68L11 is for interfacing to the AD7858/AD7858L when the supply The AD7858/ CONVERSION START AD7858L is in Interface Mode 2. The SYNC line is not used 4MHz/1.8MHz and is tied to DGND. The µController is configured as the mas- MASTER CLOCK ...
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... DOUT line (both the read and write operations would each be two 8-bit operations, one 16-bit operation for the 68HC16), wait for the conversion to be finished (= 4.6 µs for AD7858 with 4 MHz CLKIN), and then repeat the sequence. The maxi- mum serial frequency will be determined by the data access and hold times of the µ ...
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... Digital and analog ground planes should only be joined in one place. If the AD7858/AD7858L is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7858/AD7858L ...
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... DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface Mode 2 (3-Wire SPI/QSPI Interface CONFIGURING THE AD7858/AD7858L . . . . . . . . . . . . 26 Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 26 Interface Mode 2 Configuration . . . . . . . . . . . . . . . . . . . . 27 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 28 AD7858/AD7858L–8XC51 Interface . . . . . . . . . . . . . . . 28 AD7858/AD7858L–68HC11/16/L11/PIC16C42 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AD7858/AD7858L–ADSP-21xx Interface . . . . . . . . . . . . 29 AD7858/AD7858L–DSP56000/1/2/L002 Interface . . . . . 29 APPLICATION HINTS Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Evaluating the AD7858/AD7858L Performance ...
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... AD7858/AD7858L 0.02 (0.5) 0.016 (0.41) 0.01 (0.254) 0.006 (0.15) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 1.228 (31.19) 1.226 (31.14 0.260 0.001 (6.61 0.03 PIN 1 0.130 (3.30) 0.128 (3.25) 0.11 (2.79) 0.07 (1.78) SEATING PLANE 0.09 (2.28) 0.05 (1.27) NOTES 1. LEAD NO. 1 IDENTIFIED BY A DOT OR NOTCH. 2. PLASTIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS ...