AD7858 Analog Devices, AD7858 Datasheet - Page 4

• Manufacturer Part Number: AD7858
• Description: 3 V to 5 V Single Supply, 200 kSPS, 8-Channel, 12-Bit, Serial Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7858

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC

AD7858/AD7858L
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/Space ratio for the master clock input is 40/60 to 60/40.
The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
t
t
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
CLKIN
SCLK
1
2
CONVERT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CAL
CAL1
CAL2
See Table XI and timing diagrams for different interface modes and Calibration.
(see Power-Down section).
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
relinquish time of the part and is independent of the bus loading.
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
the 1.8/1 MHz master clock.
12
14
3
4
4
4
5
6
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
7
7
7
2
500
4
1.8
1
4
100
50
4.6
10 (18)
–0.4 t
50
50
75
40
20
0.4 t
0.4 t
30
30/0.4 t
50
90
50
2.5 t
2.5 t
31.25
27.78
3.47
5 V
0.4 t
Limit at T
SCLK
SCLK
CLKIN
CLKIN
SCLK
(A, B Versions)
SCLK
SCLK
MIN
, T
3 V
500
4
1.8
1
4
100
90
4.6
10 (18)
–0.4 t
90
90
115
60
30
0.4 t
0.4 t
50
50/0.4 t
50
130
90
2.5 t
2.5 t
31.25
27.78
3.47
1
MAX
0.4 t
(AV
T
A
= T
SCLK
SCLK
CLKIN
CLKIN
DD
SCLK
SCLK
= DV
MIN
SCLK
to T
DD
MAX
= +3.0 V to +5.5 V; f
Units
kHz min
MHz max
MHz max
MHz max
MHz max
ns min
ns max
µs max
µs max
ns min
ns min/max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ms typ
ms typ
ms typ
, unless otherwise noted)
Description
Master Clock Frequency
L Version, 0°C to +70°C, B Grade Only
L Version, –40°C to +85°C
CONVST Pulsewidth
CONVST↓ to BUSY↑ Propagation Delay
Conversion Time = 18 t
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t
SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
Delay from SYNC↓ Until DOUT Three-State Disabled
Delay from SYNC↓ Until DIN Three-State Disabled
Data Access Time After SCLK↓
Data Setup Time Prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
(Continuous SCLK)
Delay from SYNC↑ Until DOUT Three-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑ to BUSY↑ Delay
CONVST↓ to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(125013 t
Internal DAC Plus System Full-Scale Calibration Time, Master
Clock Dependent (111114 t
System Offset Calibration Time, Master Clock Dependent
(13899 t
CLKIN
= 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;
CLKIN
CLKIN
)
12
)
, quoted in the timing characteristics is the true bus
DD
CLKIN
) and timed from a voltage level of 1.6 V.
CLKIN
)
CLKIN