AD9122 Analog Devices, AD9122 Datasheet - Page 21

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS
Table 10. Device Configuration Register Map
Addr
(Hex)
0x00
0x01
0x03
0x04
0x05
0x06
0x07
0x08
0x0A
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x15
0x16
0x17
0x18
0x19
0x1B
Register Name
Comm
Power control
Data format
Interrupt enable
Interrupt enable
Event flag
Event flag
Clock receiver
control
PLL control
PLL control
PLL control
PLL status
PLL status
Sync control
Sync control
Sync status
Sync status
Data receiver
status
DCI delay
FIFO control
FIFO status
FIFO status
Datapath
control
PLL locked
FIFO
Warning 1
DACCLK
duty
correction
Bit 7
SDIO
Power
down
I DAC
Binary
data
format
Enable
PLL lock
lost
0
PLL lock
lost
PLL
enable
Sync
enable
Sync lost
Bypass
premod
Bandwidth[1:0]
PLL Loop
N2[1:0]
Bit 6
LSB_FIRST
Power
down
Q DAC
Q data
first
Enable
PLL
locked
0
PLL
locked
REFCLK
duty
correction
PLL
manual
enable
Data/FIFO
rate toggle
Sync
locked
FIFO
Warning 2
Bypass
sinc
−1
Power
down data
receiver
Bit 5
Reset
MSB swap
Enable
sync
signal lost
0
Sync
signal
lost
DACCLK
cross-
correction
LVDS
FRAME
level high
Bypass
NCO
Sync Phase Readback[7:0] (6.2 format)
Rev. B | Page 21 of 60
Bit 4
Power
down
aux ADC
Enable
sync
signal
locked
Enable
AED
compare
pass
Sync
signal
locked
AED
compare
pass
PLL cross-
control
enable
LVDS
FRAME
level low
REFCLK
cross-
correction
FIFO Level[7:0]
Rising
edge sync
Bit 3
Enable
AED
compare
fail
AED
compare
fail
1
LVDS DCI
level high
NCO gain
VCO Band Readback[5:0]
Sync Phase Request[5:0]
Manual VCO Band[5:0]
PLL Charge Pump Current[4:0]
N0[1:0]
Bit 2
Enable
SED
compare
fail
SED
compare
fail
1
LVDS DCI
level low
FIFO soft
align ack
Bypass
phase
comp and
dc offset
VCO Control Voltage[3:0]
FIFO Phase Offset[2:0]
Sync Averaging[2:0]
Enable
FIFO
Warning 1
FIFO
Warning 1
Bit 1
0
1
LVDS data
level high
DCI Delay[1:0]
FIFO soft
align
request
Select
sideband
Data Bus Width[1:0]
N1[1:0]
Bit 0
Enable
FIFO
Warning 2
0
FIFO
Warning 2
1
LVDS data
level low
Send
I data to
Q data
AD9122
Default
0x00
0x10
0x00
0x00
0x00
N/A
N/A
0x3F
0x40
0xD1
0xD9
N/A
N/A
0x48
0x00
N/A
N/A
0x00
0x04
N/A
N/A
0xE4
N/A