AD9122 Analog Devices, AD9122 Datasheet - Page 54

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
This completes the synchronization procedure; all devices
should now be synchronized.
To ensure that each DAC is updated with the correct data on
the same CLK edge, two timing relationships must be met on
each DAC.
•
•
When these conditions are met, the outputs of the DACs are
updated within one DAC clock cycle of each other. The timing
requirements of the input signals are shown in Figure 84.
DACCLKP(1)/
DACCLKP(2)/
Figure 84 shows the synchronization signal timing with 2×
interpolation; therefore, f
shown to be equal to the data rate. The maximum frequency at
which the device can be resynchronized in data rate mode can
be expressed as
where N is any non-negative integer.
Generally, for values of N greater than or equal to 3, select the
FIFO rate synchronization mode.
When synchronization is used in data rate mode, the timing
constraint between the DCI and DACCLK must be met according
to Table 25. In data rate mode, the allowed phase drift between
the DCI and DACCLK is limited to one DCI cycle. The DCI to
DACCLK timing restriction is required to prevent corruption of
the data transfer when the FIFO is constantly reset. The required
timing between the DCI and DACCLK is shown in Figure 85.
Table 25. DCI to DACCLK Setup and Hold Times
DCI Delay
Register 0x16,
Bits[1:0]
00
01
10
11
DACCLKN(1)
DACCLKN(2)
REFCLKP(2)/
REFCLKN(2)
FRAMEP(2)/
FRAMEN(2)
DCIP(2)/
DCIN(2)
Figure 84. Data Rate Synchronization Signal Timing Requirements,
DCIP/DCIN and D[15:0]P/D[15:0]N must meet the setup
and hold times with respect to the rising edge of DACCLK.
Synchronization (REFCLK) must also meet the setup and
hold times with respect to the rising edge of DACCLK.
f
SYNC_I
= f
t
SDCI
DATA
t
SKEW
t
Minimum Setup
Time, t
−0.07
−0.24
−0.39
−0.49
HDCI
/2
N
SDCI
2× Interpolation
DCI
(ns)
= ½ × f
t
SUSYNC
Minimum Hold
Time, t
0.82
1.13
1.40
1.55
CLK
. The REFCLK input is
t
HSYNC
HDCI
(ns)
Sampling
Interval (ns)
0.75
0.89
1.01
1.06
Rev. B | Page 54 of 60
FIFO RATE MODE SYNCHRONIZATION
The Procedure for FIFO Rate Synchronization When Directly
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in FIFO rate mode.
The procedure assumes that the DACCLK and REFCLK signals
are applied to all the devices. The procedure must be carried out
on each individual device.
Procedure for FIFO Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
Configure the AD9122 for FIFO rate, periodic synchronization
by writing 0x88 to the sync control register (Register 0x10). Addi-
tional synchronization options are available (see the Additional
Synchronization Features section).
Read the sync locked bit (Register 0x12, Bit 6) to verify that the
device is back-end synchronized. A high level on this bit indicates
that the clocks are running with a constant and known phase
relative to the synchronization signal.
Reset the FIFO by strobing the FRAME signal high for one com-
plete DCI period. Resetting the FIFO ensures that the correct data
is being read from the FIFO of each of the devices simultaneously.
This completes the synchronization procedure; all devices should
now be synchronized.
When these conditions are met, the outputs of the DACs are
updated within one DAC clock cycle of each other. The timing
requirements of the input signals are shown in Figure 86.
DACCLKP(1)/
DACCLKP(2)/
DACCLKN(1)
DACCLKN(2)
REFCLKP(2)/
REFCLKN(2)
DACCLK/
FRAMEP(2)/
FRAMEN(2)
REFCLK
DCIP(2)/
DCIN(2)
Figure 86. FIFO Rate Synchronization Signal Timing Requirements,
Figure 85. Timing Diagram for Input Data Port (Data Rate Mode)
DCI
t
SDCI
t
SKEW
SAMPLING
INTERVAL
t
SUSYNC
t
t
HDCI
DATA
2× Interpolation
t
HSYNC