AD5360 Analog Devices, AD5360 Datasheet - Page 21

• Manufacturer Part Number: AD5360
• Description: 16-Channel, 16-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5360

• Resolution (bits): 16bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

SERIAL INTERFACE
The AD5360/AD5361 contain a high speed SPI operating at
clock frequencies up to 50 MHz (20 MHz for read operations).
To minimize both the power consumption of the device and
on-chip digital noise, the interface powers up fully only when
the device is being written to, that is, on the falling edge of
SYNC . The serial interface is 2.5 V LVTTL-compatible when
operating from a 2.5 V to 3.6 V DV
four pins: SYNC (frame synchronization input), SDI (serial data
input), SCLK (clocking of data in and out of the device), and
SDO (serial data output for data readback).
SPI WRITE MODE
The AD5360/AD5361 allow writing of data via the serial inter-
face to every register directly accessible to the serial interface,
which are all registers except the X2A, X2B, and DAC registers.
The X2A and X2B registers are updated when writing to the
X1A, X1B, M, and C registers, and the DAC registers are
updated by LDAC . The serial word (see
is 24 bits long; 16 or 14 of these bits are data bits, six bits are
address bits, and two bits are mode bits that determine what
is done with the data. Two bits are reserved on the AD5361.
Table 10. AD5360 Serial Word Bit Assignation
I23
M1
Table 11. AD5361 Serial Word Bit Assignation
I23
M1
1
I1 and I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0.
I22
M0
I22
M0
I21
A5
I21
A5
I20
A4
I20
A4
I19
A3
I19
A3
I18
A2
I18
A2
CC
I17
A1
I17
A1
supply. It is controlled by
Table 10
I16
A0
I16
A0
I15
D15
I15
D13
or
Table 11
I14
D14
I14
D12
)
Rev. A | Page 21 of 28
I13
D13
I13
D11
I12
D12
I12
D10
I11
D11
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5360/AD5361 by clock pulses applied to SCLK. The first
falling edge of SYNC starts the write cycle. At least 24 falling
clock edges must be applied to SCLK to clock in 24 bits of data,
before SYNC is taken high again. If SYNC is taken high before
the 24th falling clock edge, the write operation is aborted.
If a continuous clock is used, SYNC must be taken high before
the 25th falling clock edge. This inhibits the clock within the
AD5360/AD5361. If more than 24 falling clock edges are
applied before SYNC is taken high again, the input data is
corrupted. If an externally gated clock of exactly 24 pulses is
used, SYNC may be taken high any time after the 24th falling
clock edge.
The input register addressed is updated on the rising edge of
SYNC . For another serial transfer to take place, SYNC must be
taken low again.
I11
D9
I10
D8
I10
D10
I9
D7
I9
D9
I8
D6
I8
D8
I7
D5
I7
D7
I6
D4
I6
D6
I5
D3
I5
D5
AD5360/AD5361
I4
D2
I4
D4
I3
D1
I3
D3
I2
D0
I2
D2
I1
0
I1
D1
1
I0
D0
I0
0
1