AD5360 Analog Devices, AD5360 Datasheet - Page 6

• Manufacturer Part Number: AD5360
• Description: 16-Channel, 16-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5360

• Resolution (bits): 16bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5360/AD5361
TIMING CHARACTERISTICS
DV
R
Table 3. SPI Interface (See Figure 4 and Figure 5)
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
This is measured with the load circuit shown in Figure 2
This is measured with the load circuit shown in Figure 3
L
3
4
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
CC
= 2.5 V to 5.5 V; V
1, 2
Figure 2. Load Circuit for BUSY Timing Diagram
OUTPUT
Limit at T
20
8
8
11
20
10
5
5
42
1/1.5
600
20
10
3
0
3
20/30
140
30
400
270
25
80
PIN
TO
DD
= 9 V to 16.5 V; V
r
= t
MIN
DV
f
= 2 ns (10% to 90% of DV
, T
C
50pF
CC
L
R
2.2k Ω
MAX
L
V
SS
OL
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs typ/max
ns max
ns min
ns min
μs max
ns min
μs max
μs typ/max
ns max
ns min
μs max
ns min
ns max
ns max
.
.
= −8 V to −16.5 V; V
CC
) and timed from a voltage level of 1.2 V.
Rev. A | Page 6 of 28
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time
24th SCLK falling edge to SYNC rising edge
Data setup time
Data hold time
SYNC rising edge to BUSY falling edge
BUSY pulse width low (single-channel update); see Table 8
Single-channel update cycle time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR/RESET pulse activation time
RESET pulse width low
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
RESET rising edge to BUSY falling edge
REF
= 5 V; AGND = DGND = SIGGND = 0 V; C
TO OUTPUT
PIN
Figure 3. Load Circuit for SDO Timing Diagram
50pF
C
L
200µA
200µA
MIN
I
I
OL
OH
to T
MAX
, unless otherwise noted.
V
OH
(MIN) – V
L
= 200 pF to GND;
2
OL
(MAX)