AD5662 Analog Devices, AD5662 Datasheet - Page 17
AD5662
Manufacturer Part Number
AD5662
Description
Manufacturer
Analog Devices
Datasheet
1.AD5662.pdf
(24 pages)
Specifications of AD5662
Resolution (bits)
16bit
Dac Update Rate
125kSPS
Dac Settling Time
8µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI
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AD5662 to 80C51/80L51 Interface
Figure 39 shows a serial interface between the AD5662 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows. TxD of the 80C51/80L51 drives SCLK of the AD5662,
while RxD drives the serial data line of the part. The SYNC
signal is again derived from a bit-programmable pin on the port.
In this case, port line P3.3 is used. When data is to be transmitted
to the AD5662, P3.3 is taken low. The 80C51/80L51 transmits
data in 8-bit bytes only; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5662 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.
*ADDITIONAL PINS OMITTED FOR CLARITY
80C51/80L51*
Figure 39. AD5662 to 80C51/80L51 Interface
P3.3
RxD
TxD
AD5662*
SYNC
SCLK
DIN
Rev. A | Page 17 of 24
AD5662 to MICROWIRE Interface
Figure 40 shows an interface between the AD5662 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the AD5662
on the rising edge of the SK.
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROWIRE*
Figure 40. AD5662 to MICROWIRE Interface
SO
CS
SK
AD5662*
SYNC
SCLK
DIN
AD5662