AD5346 Analog Devices, AD5346 Datasheet - Page 20

• Manufacturer Part Number: AD5346
• Description: 2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-Bit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5346

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

AD5346/AD5347/AD5348
DECODING MULTIPLE AD5346/AD5347/AD5348s
The CS pin on these devices can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same data and WR pulses, but only the CS to
one of the DACs will be active at any one time, so data will only
be written to the DAC whose CS is low.
The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state.
Figure 44 shows a diagram of a typical setup for decoding
multiple devices in a system. Once data has been written
sequentially to all DACs in a system, all the DACs can be
updated simultaneously using a common LDAC line. A com-
mon CLR line can also be used to reset all DAC outputs to 0 V.
AD5346/AD5347/AD5348 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
A digitally programmable upper/lower limit detector using two
of the DACs in the AD5346/AD5347/AD5348 is shown in
Figure 45. Any pair of DACs in the device may be used, but for
simplicity the description refers to DACs A and B.
The upper and lower limits for the test are loaded to DACs A
and B which, in turn, set the limits on the CMP04. If a signal at
the V
indicates the fail condition.
ADDRESS
ENABLE
CODED
IN
LDAC
CLR
input is not within the programmed window, an LED
WR
A0
A1
A2
Figure 44. Decoding Multiple DAC Devices
1G
1A
1B
74HC139
DGND
V
V
DD
CC
1Y0
1Y1
1Y2
1Y3
A0
A1
A2
WR
LD AC
CLR
CS
AD5346/AD5347
A0
A1
A2
WR
LD AC
CLR
CS
AD5346/AD5347
A0
A1
A2
WR
LD AC
CLR
CS
AD5346/AD5347
A0
A1
A2
WR
LD AC
CLR
CS
AD5346/AD5347
/AD5348
/AD5348
/AD5348
/AD5348
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
DATA
INPUTS
Rev. 0 | Page 20 of 24
PROGRAMMABLE CURRENT SOURCE
Figure 46 shows the AD5346/AD5347/AD5348 used as the
control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output
voltage from the DAC is applied across the current setting
resistor of 4.7 kΩ in series with the 470 Ω adjustment
potentiometer, which gives an adjustment of about ±5%.
Suitable transistors to place in the feedback loop of the ampli-
fier include the BC107 and the 2N3904, which enable the
current source to operate from a minimum V
operating range is determined by the operating characteristics
of the transistor. Suitable amplifiers include the AD820 and the
OP295, both having rail-to-rail operation on their outputs. The
current for any digital input code and resistor value can be
calculated as follows:
where:
G is the gain of the buffer amplifier (1 or 2).
D is the digital input code.
N is the DAC resolution (8, 10, or 12 bits).
R is the sum of the resistor plus adjustment potentiometer in kΩ.
*ONLY ONE CHANNEL OF V
EXT
REF
GND
V
V
REF
IN
5V
V
OUT
0.1µF
Figure 45. Programmable Window Detector
Figure 46. Programmable Current Source
V
AD5346/AD5347/
REF
0.1µF
0.1µF
AB
AD5348
I
GND
10µF
=
REF
G
V
V
V
AD5346/AD5347/
AND V
OUT
OUT
V
DD
REF
×
10µF
A
B
V
*
AD5348
V
REF
OUT
DD
V
V
GND
IN
DD
= 5V
2 ( ×
SHOWN
N
V
D
OUT
CMP04
R
*
1/2
)
mA
SOURCE
5V
1kΩ
FAIL
1/6 74HC05
PASS/
FAIL
V
of 6 V. The
SOURCE
1kΩ
PASS
LOAD
4.7kΩ
470Ω