AD5346 Analog Devices, AD5346 Datasheet - Page 9

• Manufacturer Part Number: AD5346
• Description: 2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-Bit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5346

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. AD5348 Pin Function Descriptions
TSSOP
1
2
3
4
5
6–9,
11–14
10
15
16
17
18
19
20
21–32
33
34
35
36
37
38
Pin Number
LFCSP
35
36
37
38, 39
40
1–4,
7–10
5, 6
11
12
13
14
15
16
17–28
29
30
31
32
33
34
Figure 9. AD5348 Pin Configuration—TSSOP
V
V
V
V
REF
V
REF
REF
V
V
V
V
V
V
AGND
V
DGND
REF
LDAC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Mnemonic
V
V
V
V
V
V
AGND
DGND
BUF
LDAC
A0
A1
A2
DB
CS
RD
WR
GAIN
CLR
PD
BUF
V
GH
CD
AB
A0
A1
REF
REF
REF
DD
REF
OUT
DD
EF
G
A
B
C
D
H
E
F
0
GH
EF
CD
AB
–DB
X
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
(Not to Scale)
11
AD5348
TOP VIEW
12-BIT
Function
Reference Input for DACs G and H.
Reference Input for DACs E and F.
Reference Input for DACs C and D.
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V
the same potential.
Reference Input for DACs A and B.
Output of DAC X. Buffered output with rail-to-rail operation.
Analog Ground. Ground reference for analog circuitry.
Digital Ground. Ground reference for digital circuitry.
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows
all DAC outputs to be simultaneously updated.
LSB Address Pin. Selects which DAC is to be written to.
Address Pin. Selects which DAC is to be written to.
MSB Address Pin. Selects which DAC is to be written to.
Twelve Parallel Data Inputs. DB
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with
RD to read back data from a DAC.
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
PD
CLR
GAIN
WR
RD
CS
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
A2
0
11
10
9
8
7
6
5
4
3
2
1
Rev. 0 | Page 9 of 24
11
is the MSB of these 12 bits.
V
V
V
V
V
V
V
V
AGND
AGND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
G
A
B
C
D
H
E
F
Figure 10. AD5348 Pin Configuration—LFCSP
10
1
2
3
4
5
6
7
8
9
40
11
12
39
DD
13
38
pins on the LFCSP package must be at
AD5346/AD5347/AD5348
37
14
(Not to Scale)
AD5348
TOP VIEW
36
15
12-BIT
16
35
REF
34
17
or 0 V to 2 × V
18
33
32
19
20
31
30
29
28
27
26
25
24
23
22
21
RD
CS
DB
DB
DB
DB
DB
DB
DB
DB
REF
11
10
9
8
7
6
5
4
.