AD5301 Analog Devices, AD5301 Datasheet - Page 15

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AD5301

Manufacturer Part Number
AD5301
Description
2.5 V to 5.5 V, 120 ?A, 2-Wire Interface, Voltage-Output 8-Bit DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5301

Resolution (bits)
8bit
Dac Update Rate
167kSPS
Dac Settling Time
6µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
I2C/Ser 2-wire,Ser

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WRITE OPERATION
When writing to the AD5301/AD5311/AD5321 DACs, the
user must begin with an address byte, after which the DAC
acknowledges that it is prepared to receive data by pulling
SDA
SDA
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SCL
SCL
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
MASTER
MASTER
MASTER
START
START
START
COND
COND
COND
BY
BY
BY
0
0
0
D3
D5
D7
0
0
0
D2
D4
D6
ADDRESS BYTE
ADDRESS BYTE
ADDRESS BYTE
LEAST SIGNIFICANT CONTROL BYTE
LEAST SIGNIFICANT CONTROL BYTE
LEAST SIGNIFICANT CONTROL BYTE
0
0
0
D1
D3
D5
1
1
1
D0
D2
D4
1
1
1
D1
D3
X
A1*
A1*
A1*
D0
D2
X
Figure 29. AD5301 Write Sequence
Figure 30. AD5311 Write Sequence
Figure 31. AD5321 Write Sequence
A0
A0
A0
D1
X
X
Rev. B | Page 15 of 24
R/W
R/W
R/W
D0
AD5301
X
AD5311
X
AD5321
ACK
ACK
ACK
BY
BY
BY
AD5301
AD5311
AD5321
ACK
ACK
ACK
BY
BY
BY
X
SDA low. This address byte is followed by the 16-bit word in the
form of two control bytes. The write operations for the three
DACs are shown in Figure 29 to Figure 31.
X
X
MASTER
MASTER
MASTER
MOST SIGNIFICANT CONTROL BYTE
COND
MOST SIGNIFICANT CONTROL BYTE
COND
COND
STOP
MOST SIGNIFICANT CONTROL BYTE
STOP
STOP
BY
BY
BY
X
X
X
PD1
PD1
PD1
PD0
PD0
PD0
D11
D7
D9
AD5301/AD5311/AD5321
D10
D6
D8
D5
D7
D9
D4
D6
D8
AD5301
AD5311
AD5321
ACK
ACK
ACK
BY
BY
BY

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