AD5301 Analog Devices, AD5301 Datasheet - Page 16

• Manufacturer Part Number: AD5301
• Description: 2.5 V to 5.5 V, 120 ?A, 2-Wire Interface, Voltage-Output 8-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5301

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5301/AD5311/AD5321
READ OPERATION
When reading data back from the AD5301/AD5311/AD5321
DACs, the user must begin with an address byte after which
the DAC acknowledges that it is prepared to transmit data by
pulling SDA low. There are two different read operations. In the
case of the AD5301, the readback is a single byte that consists of
SDA
SCL
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
MASTER
MASTER
START
COND
START
COND
BY
MASTER
BY
START
COND
0
BY
0
0
D5
0
D7
ADDRESS BYTE
0
0
D4
D6
0
LEAST SIGNIFICANT CONTROL BYTE
ADDRESS BYTE
LEAST SIGNIFICANT BYTE
0
0
D3
D5
1
ADDRESS BYTE
1
1
D2
D4
1
1
1
D1
A1*
D3
A1*
A1*
A0
Figure 32. AD5301 Readback Sequence
Figure 33. AD5311 Readback Sequence
Figure 34. AD5321 Readback Sequence
D0
D2
A0
R/W
A0
D1
X
Rev. B | Page 16 of 24
AD5301
R/W
AD5311
R/W
ACK
BY
ACK
BY
AD5321
D0
X
ACK
BY
MASTER
NO ACK
MASTER
NO ACK
D7
BY
BY
the eight data bits in the DAC register. However, in the case
of the AD5311 and AD5321, the readback consists of two bytes
that contain both the data and the power-down mode bits. The
read operations for the three DACs are shown in Figure 32 to
Figure 34.
X
X
D6
MASTER
MASTER
COND
STOP
COND
STOP
BY
BY
MOST SIGNIFICANT BYTE
X
X
D5
MOST SIIGNIFICANT BYTE
PD1
PD1
DATA BYTE
D4
PD0
PD0
D3
D11
D9
D2
D10
D8
D1
D7
D9
D0
MASTER
NO ACK
D6
AD5311
D8
BY
ACK
BY
MASTER
COND
STOP
BY
MASTER
COND
STOP
BY