AD9767 Analog Devices, AD9767 Datasheet
AD9767
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AD9767 Summary of contents
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... Each DAC provides differential current output, thus supporting single-ended or dif- ferential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%. ...
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... Revision History: AD9763 1/08—Rev Rev. E Combined with AD9765 and AD9767 Data Sheets.......Universal Changes to Figure 1...........................................................................1 Changes to Applications Section.....................................................1 Changes to Timing Diagram Section .............................................7 Added Figure 4 and Figure 5............................................................9 Changes to Table 6.......................................................................... 10 Change to Typical Performance Characteristics Section Conditions Statement ...
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... Changes to Figure 29 ......................................................................21 2/00—Rev Rev. B 12/99—Rev Rev. A Revision History: AD9765 1/08—Rev Rev. E Combined with AD9763 and AD9767 Data Sheets ...... Universal Changes to Figure 1...........................................................................1 Changes to Applications Section.....................................................1 Changes to Timing Diagram Section .............................................7 Change to Absolute Maximum Ratings .........................................8 Added Figure 3 and Figure 5 ...........................................................9 Changes to Table 6 ...
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... AD9763/AD9765/AD9767 Changes to Dual-Port Mode Timing ........................................... 24 Changes to Interleaved Mode Timing Section ........................... 25 Added Figure 64.............................................................................. 25 Change to Differential Coupling Using a Transformer Section......28 Changes to Power and Grounding Considerations Section............30 Added Figure 79 and Figure 81..................................................... 31 Added to Quadrature Amplitude Modulation (QAM) Example Using the AD9763 Section ............................................ 32 Added Figure 83 and Figure 84..................................................... 32 Changes to CDMA Section ...
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... REF = 20 mA and Ω and LOAD OUTA OUTB CLK Rev Page AD9763/AD9765/AD9767 AD9767 Max Min Typ Max 14 +1.5 −3.5 ±1.5 +3.5 +2.0 −4.0 +4.0 +0.75 −2.5 ±1.0 +2.5 +1.0 −3.0 +3.0 +0.02 −0.02 +0.02 +2 − ...
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... Rev Page Data Sheet AD9767 Max Min Typ Max Unit 125 MSPS pV-s 2 pA/√Hz 30 pA/√ dBc 77 dBc 73 dBc ...
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... OUTFS Min 3.5 2.1 0 −10 −10 2.0 1.5 3 DATA IN I OUTA OR I OUTB t PD Figure 2. Timing Diagram for Dual and Interleaved Modes Rev Page AD9763/AD9765/AD9767 Typ Max Unit 1.3 V 0.9 V +10 μA +10 μ LPW ...
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... AD9763/AD9765/AD9767 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To AVDD ACOM DVDD1, DVDD2 DCOM1/DCOM2 ACOM DCOM1/DCOM2 AVDD DVDD1/DVDD2 MODE, DCOM1/DCOM2 CLK1/IQCLK, CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL Digital Inputs DCOM1/DCOM2 ACOM OUTA1 OUTA2 I /I OUTB1 OUTB2 REFIO, FSADJ1, ACOM FSADJ2 GAINCTRL, SLEEP ACOM Junction ...
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... DB9P2 25 Rev Page AD9763/AD9765/AD9767 DB0P2 (LSB) PIN 1 DB1P2 35 DB2P2 34 DB3P2 33 DB4P2 32 AD9767 DB5P2 31 TOP VIEW (Not to Scale) DB6P2 30 DB7P2 29 DB8P2 28 DB9P2 27 26 DB10P2 25 DB11P2 Figure 5. AD9767 Pin Configuration ...
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... AD9763/AD9765/AD9767 Table 6. Pin Function Descriptions Pin No. AD9763 AD9765 AD9767 14, 13, 14, N 35, 36 15, 21 15, 21 15, 21 16, 22 16 39, 40 39, 40 39, 40 ...
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... OUT Figure 8. SFDR vs MSPS OUT = 20 mA, 50 Ω doubly terminated load, differential output, T OUTFS f = 125MSPS CLK 100 2.0 2.5 –6dBFS Rev Page AD9763/AD9765/AD9767 = 25°C, SFDR up to Nyquist 0dBFS 75 –6dBFS 70 –12dBFS (MHz) OUT Figure 9 ...
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... AD9763/AD9765/AD9767 85 910kHz/10MSPS 80 2.27MHz/25MSPS 75 70 5.91MHz/65MSPS –20 –16 –12 –8 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 85 5MHz/25MSPS 80 1MHz/5MSPS 75 2MHz/10MSPS 70 65 13MHz/65MSPS 60 55 –20 –16 –12 –8 A (dBFS) OUT Figure 13. Single-Tone SFDR vs. A OUT 80 3.38MHz/3.36MHz @ 25MSPS 0.965MHz/1.035MHz @ 7MSPS 75 6.75MHz/7.25MHz @ 65MSPS ...
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... Figure 20. Single-Tone SFDR @ 100 = 125 MSPS, 0 dBFS 1.0 0.5 0 –0.5 –1 125 MSPS CLK 125 MSPS CLK Rev Page AD9763/AD9765/AD9767 0 –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY (MHz) Figure 21. Dual-Tone SFDR @ f = 125 MSPS CLK 0 – ...
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... AD9763/AD9765/AD9767 AD9765 AVDD = 3 DVDD = 3 Nyquist, unless otherwise noted 5MSPS CLK f = 25MSPS CLK 65MSPS CLK (MHz) OUT Figure 23. SFDR vs dBFS OUT 95 90 0dBFS 85 –6dBFS 80 75 1.00 1.25 1.50 1.75 f (MHz) OUT Figure 24. SFDR vs MSPS OUT ...
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... OUT CLK – OUT CLK 0.05 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 –0.35 – OUT CLK Rev Page AD9763/AD9765/AD9767 20mA OUTFS 10mA OUTFS 5mA OUTFS 100 f (MSPS) CLK Figure 32. SINAD vs. f and I ...
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... AD9763/AD9765/AD9767 1MHz OUT 10MHz OUT 25MHz OUT 40MHz 60 OUT 60MHz OUT 50 45 –60 –40 – TEMPERATURE (°C) Figure 35. SFDR vs. Temperature @ 125 MSPS, 0 dBFS 0.05 0.03 GAIN ERROR OFFSET ERROR 0 –0.03 –0.05 –40 – TEMPERATURE (°C) Figure 36. Gain and Offset Error vs. Temperature @ f ...
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... OUT Figure 42. SFDR vs MSPS OUT = 20 mA, 50 Ω doubly terminated load, differential output, T OUTFS = 125MSPS 100 –6dBFS 2 Rev Page AD9763/AD9765/AD9767 = 25°C, SFDR 0dBFS 75 –6dBFS 70 –12dBFS (MHz) OUT Figure 43 ...
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... AD9763/AD9765/AD9767 90 910kHz/10MSPS 85 2.27MHz/25MSPS 11.37MHz/125MSPS 65 5.91MHz/65MSPS 60 –20 –15 –10 A (dBFS) OUT Figure 46. Single-Tone SFDR vs. A OUT 90 1MHz/5MSPS 85 2MHz/10MSPS 80 75 5MHz/25MSPS 70 65 13MHz/65MSPS –20 –15 –10 A (dBFS) OUT Figure 47. Single-Tone SFDR vs. A OUT 85 0.965MHz/1.035MHz@7MSPS 80 3.38MHz/3.63MHz@25MSPS 16.9MHz/18.1MHz@125MSPS 60 6.75MHz/7.25MHz@65MSPS ...
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... FREQUENCY (MHz) Figure 54. Single-Tone SFDR @ 100 1.0 0.5 0 –0.5 –1 125 MSPS CLK 125 MSPS CLK Rev Page AD9763/AD9765/AD9767 0 –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY (MHz) Figure 55. Dual-Tone SFDR @ f = 125 MSPS CLK 0 –10 – ...
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... AD9763/AD9765/AD9767 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code ...
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... REF WRT1/ GAINCTRL IQWRT DVDD1/DVDD2 50Ω DCOM1/DCOM2 RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR Figure 57. Basic AC Characterization Test Setup for AD9763/AD9765/AD9767, Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2 R 1 SET 2kΩ FSADJ1 I 1 REF 0.1µF REFIO ...
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... DAC1 and DAC2 are set to the same value using one R for both DAC1 and DAC2 is set via the FSADJ1 terminal. SETTING THE FULL-SCALE CURRENT Both of the DACs in the AD9763/AD9765/AD9767 contain a control amplifier that is used to regulate the full-scale output current (I converter, as shown in Figure 59, so that its current output (I ...
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... OUTFS swing at I OUTFS unipolar output is desired, select IOUTA. OUTFS The distortion and noise performance of the AD9763/AD9765/ AD9767 can be enhanced when it is configured for differential operation. The common-mode error sources of both I I can be significantly reduced by the common-mode rejection OUTB ). This is nominally REF of a transformer or differential amplifier ...
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... DB9P1 and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765, and DB13P1 and DB13P2 for the AD9767, and the least significant bits (LSBs) are DB0P1 and DB0P2 for all three parts full-scale output current when all data bits are at Logic 1 ...
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... Data Sheet Interleaved Mode Timing When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767 operate in interleaved mode (refer to Figure 61). In addition, WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2 functions as IQSEL, and CLK2 functions as IQRESET. Data enters the device on the rising edge of IQWRT. The logic level of IQSEL steers the data to either Channel Latch 1 (IQSEL = Channel Latch 2 (IQSEL = 0) ...
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... The external clock driver circuitry provides the AD9763/AD9765/ AD9767 with a low-jitter clock input meeting the minimum and maximum logic levels while providing fast edges. Fast clock edges help minimize jitter manifesting itself as phase noise on a reconstructed waveform ...
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... RATIO ( / OUT CLK Figure 70. I vs. Ratio @ DVDD1 = DVDD2 = 5 V DVDD Rev Page AD9763/AD9765/AD9767 18 125MSPS 16 14 100MSPS 12 10 65MSPS 8 6 25MSPS 4 5MSPS 0.1 0.2 0 RATIO ( / ) OUT CLK Figure 71. I vs. Ratio @ DVDD1 = DVDD2 = 3.3 V DVDD 0 ...
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... The differential circuit shown in Figure 74 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9763/AD9765/AD9767 and the op amp, is used to level shift the differential output of the AD9763/AD9765/AD9767 to midsupply (that is, AVDD/2). The for this application ...
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... OPT 25Ω 25Ω Figure 74. Single-Supply DC Differential-Coupled Circuit SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT Figure 75 shows the AD9763/AD9765/AD9767 configured to provide a unipolar output range of approximately 0.5 V for a doubly terminated 50 Ω cable, because the nominal full- scale current ( flows through the equivalent OUTFS Ω ...
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... OUT IN Proper grounding and decoupling are primary objectives in any high speed, high resolution system. The AD9763/AD9765/AD9767 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents . PSRR is very code in a system. In general, decouple the analog supply (AVDD) to the analog common (ACOM) as close to the chip as physically possible ...
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... Figure 81. AD9765 Notch in Missing Bin at 5 MHz Is Down >60 dB –20 –40 –60 –80 –100 0.785 0.805 0.825 –120 Figure 82. AD9767 Notch in Missing Bin at 5 MHz Is Down >60 dB Rev Page AD9763/AD9765/AD9767 –20 –30 –40 –50 –60 –70 –80 –90 0.665 0.685 ...
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... AD8346 via matching networks. ACOM AVDD OUT DAC OUT LA RL AD9763/ RL AD9765/ AD9767 OUT DAC FILTER OUT RL RL VDIFF = 1.82V p-p FSADJ2 REFIO DIFFERENTIAL RLC FILTER RL = 200Ω ...
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... ACP to be above the spectral mask, filtering or different component selection is needed to meet the mask requirements. Figure 85 shows the results of using the AD9763/AD9765/ AD9767 with the AD8346 to reconstruct a wideband CDMA signal centered at 2.4 GHz. The baseband signal is sampled at 65 MSPS and has a chip rate of 8 MHz. ...
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... INP36 8 9 INCK2 10 Figure 86. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board (1) This board allows the user the flexibility to operate the AD9763/ AD9765/AD9767 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single-ended and differential outputs. The digital inputs can be ...
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... Data Sheet Figure 87. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board ( RC0603 CC0805 CC0805 Rev Page AD9763/AD9765/AD9767 00617-091 RC0805 RC0805 RC0805 RC0805 RC0805 ...
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... C26 100PF C25 100PF DNP R26 51 C32 RC0603 DNP JP20 CC0805 DNP R25 51 R24 RC0603 Figure 88. Modulator on AD9763/AD9765/AD9767 Evaluation Board Rev Page DNP DNP RC0603 MODULATED OUTPUT AGND2;3,4,5 R27 0 SMAEDGE C28 J1 RC0603 100PF AVDD2 2 TP6 RED AVDD2 R28 1K AGND2 ...
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... Data Sheet RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 89. Digital Input Signaling (1) Rev Page AD9763/AD9765/AD9767 00617-093 ...
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... AD9763/AD9765/AD9767 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RIBBON RA Figure 90. Digital Input Signaling (2) Rev Page Data Sheet 00617-087 ...
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... Data Sheet RC07CUP RC0805 RC0805 CC0805 CC0805 RC07CUP RC0805 RC0805 Figure 91. Device Under Test/Analog Output Signal Conditioning Rev Page AD9763/AD9765/AD9767 00617-088 ...
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... AD9763/AD9765/AD9767 EVALUATION BOARD LAYOUT Figure 92. Assembly, Top Side Rev Page Data Sheet ...
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... Data Sheet Figure 93. Assembly, Bottom Side Rev Page AD9763/AD9765/AD9767 ...
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... AD9763-EBZ AD9765AST –40°C to +85°C AD9765ASTRL –40°C to +85°C AD9765ASTZ –40°C to +85°C AD9765ASTZRL –40°C to +85°C AD9765-EBZ AD9767ASTZ –40°C to +85°C AD9767ASTZRL –40°C to +85°C AD9767-EBZ RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0. PIN 1 TOP VIEW ...
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... Data Sheet NOTES AD9763/AD9765/AD9767 Rev Page ...
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... AD9763/AD9765/AD9767 NOTES ©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00617-0-8/11(G) Rev Page Data Sheet ...