AD9767 Analog Devices, AD9767 Datasheet - Page 26

• Manufacturer Part Number: AD9767
• Manufacturer: Analog Devices

Specifications of AD9767

• Resolution (bits): 14bit
• Dac Update Rate: 125MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9763/AD9765/AD9767
Because the AD9763/AD9765/AD9767 is capable of being clocked
up to 125 MSPS, the quality of the clock and data input signals
are important in achieving the optimum performance. Operating
the AD9763/AD9765/AD9767 with reduced logic swings and a
corresponding digital supply (DVDD1/DVDD2) results in the
lowest data feedthrough and on-chip digital noise. The drivers of
the digital data interface circuitry should be specified to meet the
minimum setup and hold times of the AD9763/AD9765/AD9767
as well as its required minimum and maximum input logic level
thresholds.
Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion
of a low value (that is, 20 Ω to 100 Ω) resistor network between
the AD9763/AD9765/AD9767 digital inputs and driver outputs
can be helpful in reducing any overshooting and ringing at the
digital inputs that contribute to digital feedthrough. For longer
board traces and high data update rates, stripline techniques
with proper impedance and termination resistors should be
considered to maintain “clean” digital inputs.
The external clock driver circuitry provides the AD9763/AD9765/
AD9767 with a low-jitter clock input meeting the minimum
and maximum logic levels while providing fast edges. Fast clock
edges help minimize jitter manifesting itself as phase noise on a
reconstructed waveform. Therefore, the clock input should be
driven by the fastest logic family suitable for the application.
Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This
typically results in a slight degradation in the phase noise, which
becomes more noticeable at higher sampling rates and output
frequencies. In addition, at higher sampling rates, the 20%
tolerance of the digital logic threshold should be considered,
because it affects the effective clock duty cycle and,
subsequently, cuts into the required data setup and hold times.
Input Clock and Data Timing Relationship
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9763/AD9765/AD9767 are rising
edge triggered and therefore exhibit SNR sensitivity when the
data transition is close to this edge. The goal when applying the
AD9763/AD9765/AD9767 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 68 shows the relationship of SNR
to clock placement with different sample rates. Note that at the
lower sample rates, much more tolerance is allowed in clock
placement; much more care must be taken at higher rates.
Rev. G | Page 26 of 44
SLEEP MODE OPERATION
The AD9763/AD9765/AD9767 has a power-down function that
turns off the output current and reduces the supply current to less
than 8.5 mA over the specified supply range of 3.3 V to 5 V and
over the full operating temperature range. This mode can be
activated by applying a Logic Level 1 to the SLEEP pin. The
SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital
input also contains an active pull-down circuit that ensures the
AD9763/AD9765/AD9767 remains enabled if this input is left
disconnected. The AD9763/AD9765/AD9767 require less than
50 ns to power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation (P
dependent on several factors, including
•
•
•
•
The power dissipation is directly proportional to the analog
supply current (I
I
and is insensitive to f
Conversely, I
the f
and Figure 71 show I
output ratios (f
DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively. Note
that I
DVDD1/DVDD2 is reduced from 5 V to 3.3 V.
AVDD
Figure 68. SNR vs. Clock Placement @ f
CLK
the power supply voltages (AVDD and DVDD1/DVDD2)
the full-scale current output (I
the update rate (f
the reconstructed digital input waveform
DVDD
is directly proportional to I
, and the digital supply (DVDD1/DVDD2). Figure 70
80
70
60
50
40
30
20
10
0
–4
is reduced by more than a factor of 2 when
AD9763
AD9765
AD9767
DVDD
OUT
–3
AVDD
/f
is dependent on the digital input waveform,
CLK
TIME OF DATA CHANGE RELATIVE TO
) and the digital supply current (I
CLK
DVDD
–2
) for various update rates with DVDD1 =
CLK
.
RISING CLOCK EDGE (ns)
)
D
as a function of full-scale sine wave
) of the AD9763/AD9765/AD9767 is
–1
OUTFS,
0
OUT
OUTFS
= 20 MHz and f
as shown in Figure 69,
1
)
2
Data Sheet
CLK
3
= 125 MSPS
DVDD
4
).