AD9767 Analog Devices, AD9767 Datasheet - Page 24

• Manufacturer Part Number: AD9767
• Manufacturer: Analog Devices

Specifications of AD9767

• Resolution (bits): 14bit
• Dac Update Rate: 125MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9763/AD9765/AD9767
I
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the
AD9763/AD9765/AD9767.
The positive output compliance range is slightly dependent on
the full-scale output current, I
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at I
does not exceed 0.5 V. Applications requiring the AD9763/
AD9765/AD9767 output (that is, V
output compliance range must size R
beyond this compliance range adversely affects the linearity
performance of the AD9763/AD9765/AD9767 and
subsequently degrades its distortion performance.
DIGITAL INPUTS
The digital inputs of the AD9763/AD9765/AD9767 consist of
two independent channels. For the dual-port mode, each DAC has
its own dedicated 10-/12-/14-bit data port: WRT line and CLK line.
In the interleaved timing mode, the function of the digital control
pins changes as described in the Interleaved Mode Timing
section. The 10-/12-/14-bit parallel data inputs follow straight
binary coding, where the most significant bits (MSBs) are DB9P1
and DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765,
and DB13P1 and DB13P2 for the AD9767, and the least significant
bits (LSBs) are DB0P1 and DB0P2 for all three parts. I
a full-scale output current when all data bits are at Logic 1. I
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
DAC TIMING
The AD9763/AD9765/AD9767 can operate in two timing modes,
dual and interleaved, which are described in the following
sections. The block diagram in Figure 61 represents the latch
architecture in the interleaved timing mode.
OUTA
and I
OUTB
also have a negative and positive voltage
OUTFS
OUTA
. When I
LOAD
and/or V
accordingly. Operation
OUTFS
OUTB
is decreased
OUTA
) to extend its
OUTA
and I
produces
OUTB
OUTB
Rev. G | Page 24 of 44
Dual-Port Mode Timing
When the MODE pin is at Logic 1, the AD9763/AD9765/AD9767
operates in dual-port mode (refer to Figure 57). The AD9763/
AD9765/AD9767 functions as two distinct DACs. Each DAC
has its own completely independent digital input and control lines.
The AD9763/AD9765/AD9767 features a double-buffered data
path. Data enters the device through the channel input latches.
This data is then transferred to the DAC latch in each signal
path. After the data is loaded into the DAC latch, the analog
output settles to its new value.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK must occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns must be
maintained from the rising edge of WRT to the rising edge of CLK.
Timing specifications for dual-port mode are shown in Figure 62
and Figure 63.
IQWRT
IQSEL
DATA IN, PORT 1
WRT1/WRT2
CLK1/CLK2
WRT1/WRT2
INTERLEAVED
CLK1/CLK2
DATA IN
DATA IN
I
I
OUTA
OUTB
IQRESET
I
I
OUTA
OUTB
OR
IQCLK
OR
Figure 61. Latch Structure in Interleaved Mode
D1
Figure 62. Dual-Port Mode Timing
Figure 63. Dual-Port Mode Timing
XX
D2
PORT 1
PORT 2
LATCH
LATCH
INPUT
INPUT
÷2
t
S
D1
D3
DAC1
LATCH
DAC2
LATCH
t
PD
D2
D4
DAC1
DAC2
t
H
t
t
LPW
CPW
Data Sheet
DEINTERLEAVED
DATA OUT
D3
D5
D4