AD8804 Analog Devices, AD8804 Datasheet
AD8804
Specifications of AD8804
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AD8804 Summary of contents
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... DAC latches to be loaded with the last 8 bits of data. The AD8802/ AD8804 consumes only 10 A from 5 V power supplies. In ad- dition, in shutdown mode reference input current consumption is also reduced while saving the DAC latch settings for use after return to normal operation ...
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... DD T +85 C unless otherwise noted) A Symbol Conditions N DNL Guaranteed Monotonic INL G FSE V ZSE R OUT R REFH V Pin Available on AD8804 Only REFL R Digital Inputs = REFH H REFH R Digital Inputs = REFL H REFL C Digital Inputs all Zeros REF0 C Digital Inputs all Ones REF1 ...
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... TOP VIEW O5 6 (Not to Scale SHDN MAX – GND AD8804 PIN DESCRIPTIONS Pin Name Description 1 V Common High-Side DAC Reference Input REFH 2 O1 DAC Output #1, addr = 0000 DAC Output #2, addr = 0001 4 O3 DAC Output #3, addr = 0010 ...
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... AD8802/AD8804–Typical Performance Characteristics + +5V REFH REFL 0.5 0.25 0 –0.25 –0.5 –0.75 – 128 160 CODE – Decimal Figure 1. INL vs. Code 1 0. + +5V REFH REFL 0.25 0 –0.25 –0.5 –0.75 – 128 160 CODE – Decimal Figure 2 ...
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... OUT1 5mV/DIV CS 5V/DIV 10k 100k 0.01 5µs 0.005 + +5V REF –0.005 –0.01 0 Figure 12. Zero-Scale Error Accelerated by Burn-In –5– AD8802/AD8804 OUTPUT1 +5V DD 100 V = +5V REF 1MHz 10 0% 10mV 200ns TIME – 0.2µs/DIV 5mV 1µs 100 ...
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... Input) pin. The format of this data word is four address bits, MSB first, followed by 8 data bits, MSB first. Table I provides the serial register data word format. The AD8802/AD8804 has the following address assignments for the ADDR decode which determines the location of the DAC register receiving the serial ...
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... SHDN 2R LSB 2R DIGITAL INTERFACING The AD8802/AD8804 contains a standard three-wire serial in the follow- put control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If ...
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... REFL Figure 22. Buffering the AD8802/AD8804 Output Increasing Output Voltage Swing An external amplifier can also be used to extend the output volt- age swing beyond the power supply rails of the AD8802/AD8804. AD8802/ This technique permits an easy digital interface for the DAC, AD8804 while expanding the output swing to take advantage of higher voltage external power supplies. For example, DAC A of Fig- ure 23 is configured to swing from – ...
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... Twelve data bits are required to load a value into the AD8802/ AD8804 (4 bits for the DAC address and 8 bits for the DAC value). If more than 12 bits are transmitted before the Chip Se- lect input goes high, the extra (i.e., the most-significant) bits are ignored ...
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... VALU_WAIT: JNB CLR SETB RET ; BYTESWAP: MOV SWAP_LOOP: MOV RLC MOV MOV RRC MOV DJNZ RET END Listing 1. Software for the 8051 to AD8802/AD8804 Serial Port Interface 8051 µC P1.7 P1.6 P1.5 P1.4 PORT 1 1.7 1.6 1.5 1.4 Figure 25. An AD8802/AD8804-8051 C Interface Using Parallel Port 1 90H 40H 41H 042H 043H ...
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... This 8051 C subroutine loads an AD8802 or AD8804 DAC with an 8-bit value, ; using the 8051’s parallel port #1. ; The DAC value is stored at location DAC_VALUE ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations PORT1 DATA DAC_VALUE DATA DAC_ADDR DATA LOOPCOUNT DATA ; ORG LD_8804: ORL ...
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... SPI data register; Read-Buffer; Write-Shifter SDI1 is encoded from SDI2 is encoded from 00H to FFH AD8802/AD8804 requires two 8-bit loads; upper 4 bits of SDI1 are ignored. AD8802/AD8804 address bits in last four LSBs of SDI1. SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0” SDI packed byte 2 “DB7–DB4;DB3–DB0” ...
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... STAA SDI1 * * Enter Contents of SDI2 Data Register * LDAA $0001 STAA SDI2 * LDX #SDI1 LDY #$1000 * * Reset AD8802 to one-half scale (AD8804 does not have a Reset input) * BCLR PORTC,Y $02 BSET PORTC,Y $ Get AD8802/04 ready for data input * BCLR PORTD,Y $02 * TFRLP LDAA 0,X STAA ...
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... Now notice that the normal + GND voltage range of the AD8802/AD8804 does not cover the 3 –1.2 V operational gain control range of the SSM2018T. To cover the operating gain range fully and not exceed the maxi- mum specified power supply rating requires the O1 output of AD8802/AD8804 to be level shifted down ...
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... V within the common-mode range accomplish this, place V 1.0 V, then all 256 voltage levels of the AD8804 will fall within the gain-control range of the AD603. Please refer to the AD603 data sheet for further information regarding gain control, layout, and general operation ...
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... AD603 3 7 100 REF195 +5.0V OUT GND 1µ AD8804 REFL REFH SDI CLK CS GND SHDN TO µC Figure 30. A Low Noise 90 MHz PGA OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 0.512 (13.00) 0.496 (12.60) 20 0.32 (8.128) 0.135 (3.429) 0.30 (7.62) 0.125 (3.17) 1 ...