AD8804 Analog Devices, AD8804 Datasheet - Page 6

• Manufacturer Part Number: AD8804
• Description: 12 Channel, 8-Bit TrimDACs with Power Shutdown & Separate VREFL Input
• Manufacturer: Analog Devices

Specifications of AD8804

• Resolution (bits): 8bit
• Dac Update Rate: 1.7MSPS
• Dac Settling Time: 600ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD8802/AD8804
OPERATION
The AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6 s (13
30 ns). The exact timing requirements are shown in Figure 15.
ADDR
B11 B10 B9 B8
A3
MSB
2
The AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a V
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and V
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
11
Figure 13. Full-Scale Error Accelerated by Burn-In
A2
2
REF
10
–0.02
–0.04
0.04
0.02
DAC# = A3
inputs. In shutdown mode the DACX register settings
0
A1 A0
2
0
9
Table I. Serial-Data Word Format
LSB MSB
2
100
8
REFH
HOURS OF OPERATION AT 150 C
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
2
8 + A2
7
200
and a V
x – 2
x + 2
DATA
2
6
x
300
4 + A1
2
REFL
5
pin to establish indepen-
2
400
4
2 + A0 + 1
V
V
SS = 176 PCS
DD
REF
2
3
= +4.5V
= +4.5V
500
2
2
600
2
12
1
LSB
2
0
–6–
Figure 14. REF Input Resistance Accelerated by Burn-In
(DATA IN)
DETAIL SERIAL DATA INPUT TIMING ( R S = "1")
V
CLK
OUT
SDI
V
CS
CLK
SDI
OUT
CS
+5V
–0.5
–1.0
0V
+5V
1.0
0.5
1
0
1
0
1
0
0V
RESET TIMING
V
0
1
0
1
0
1
0
OUT
0
RS
Figure 15b. Detail Timing Diagram
Figure 15c. Reset Timing Diagram
2.5V
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
+5V
A
Figure 15a. Timing Diagram
X
1
0
OR D
t
100
CSS
X
t
HOURS OF OPERATION AT 150 C
CH
x + 2
200
1 LSB ERROR BAND
A
t
X
DS
t
x – 2
OR D
CL
t
RS
x
300
DAC REGISTER LOAD
X
t
DH
1/2 LSB ERROR BAND
t
S
t
CSH
400
V
V
CODE = 55
SS = 176 PCS
DD
REF
t
CS1
= +4.5V
= +4.5V
t
1 LSB
500
S
t
CSW
H
600
1/2 LSB
REV. 0